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Cheng-Kok Koh Vis

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*2009
88EEWenwen Chai, Dan Jiao, Cheng-Kok Koh: A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction. DAC 2009: 752-757
87EECheng-Kok Koh, Weng-Fai Wong, Yiran Chen, Hai Li: Tolerating process variations in large, set-associative caches: The buddy cache. TACO 6(2): (2009)
2008
86EEKalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan: Guiding global placement with wire density. ICCAD 2008: 212-217
85EEJitesh Jain, Hong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan: A fast band matching technique for impedance extraction. ISCAS 2008: 2981-2984
84EEKuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao: Optimal post-routing redundant via insertion. ISPD 2008: 111-117
83EEKuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao: Fast and Optimal Redundant Via Insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2197-2208 (2008)
2007
82EERuilin Wang, Cheng-Kok Koh: A frequency-domain technique for statistical timing analysis of clock meshes. ICCAD 2007: 334-339
81EEHong Li, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan: A fast band-matching technique for interconnect inductance modeling. ICCAD 2007: 568-571
80EEWeng-Fai Wong, Cheng-Kok Koh, Yiran Chen, Hai Li: VOSCH: Voltage scaled cache hierarchies. ICCD 2007: 496-503
79EEYiran Chen, Hai Li, Jing Li, Cheng-Kok Koh: Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI. ISLPED 2007: 195-200
78EEHong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen: Statistical Timing Analysis Considering Spatial Correlations. ISQED 2007: 102-107
77EEHong Li, Jitesh Jain, Venkataramanan Balakrishnan, Cheng-Kok Koh: Efficient Analysis of Large-Scale Power Grids Based on a Compact Cholesky Factorization. ISQED 2007: 627-632
76EEChen Li, Cheng-Kok Koh: Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement. ISQED 2007: 829-834
75EERuibing Lu, Aiqun Cao, Cheng-Kok Koh: SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. IEEE Trans. VLSI Syst. 15(1): 69-79 (2007)
74EEChen Li, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden: Routability-Driven Placement and White Space Allocation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 858-871 (2007)
2006
73EEHai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh: SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design. ASP-DAC 2006: 158-163
72EEJitesh Jain, Stephen Cauley, Cheng-Kok Koh, Venkataramanan Balakrishnan: SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices. ASP-DAC 2006: 422-427
71EEYa-Chi Yang, Cheng-Kok Koh, Venkataramanan Balakrishnan: Adaptive admittance-based conductor meshing for interconnect analysis. ASP-DAC 2006: 509-514
70EEHong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh: Stable and compact inductance modeling of 3-D interconnect structures. ICCAD 2006: 1-6
69EEAiqun Cao, Ruibing Lu, Chen Li, Cheng-Kok Koh: Postlayout optimization for synthesis of Domino circuits. ACM Trans. Design Autom. Electr. Syst. 11(4): 797-821 (2006)
68EERuibing Lu, Cheng-Kok Koh: Performance analysis of latency-insensitive systems. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 469-483 (2006)
2005
67EEJacob R. Minz, Sung Kyu Lim, Cheng-Kok Koh: 3D module placement for congestion and power noise reduction. ACM Great Lakes Symposium on VLSI 2005: 458-461
66EERuibing Lu, Aiqun Cao, Cheng-Kok Koh: Improving the scalability of SAMBA bus architecture. ASP-DAC 2005: 1164-1167
65EEAiqun Cao, Ruibing Lu, Cheng-Kok Koh: Post-layout logic duplication for synthesis of domino circuits with complex gates. ASP-DAC 2005: 260-265
64EEChen Li, Cheng-Kok Koh, Patrick H. Madden: Floorplan management: incremental placement for gate sizing and buffer insertion. ASP-DAC 2005: 349-354
63EEHong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh, Guoan Zhong: Compact and stable modeling of partial inductance and reluctance matrices. ASP-DAC 2005: 507-510
62EEWai-Ching Douglas Lam, Cheng-Kok Koh: Process variation robust clock tree routing. ASP-DAC 2005: 606-611
61EEYongxin Zhu, Weng-Fai Wong, Cheng-Kok Koh: A Performance and Power Co-optimization Approach for Modern Processors. CIT 2005: 822-828
60 Wai-Ching Douglas Lam, J. Jam, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen: Statistical based link insertion for robust clock network design. ICCAD 2005: 588-591
59EEYiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh: Cascaded carry-select adder (C2SA): a new structure for low-power CSA design. ISLPED 2005: 115-118
58EEAiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy: Synthesis of skewed logic circuits. ACM Trans. Design Autom. Electr. Syst. 10(2): 205-228 (2005)
57EEYiran Chen, Kaushik Roy, Cheng-Kok Koh: Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors. IEEE Trans. VLSI Syst. 13(1): 75-85 (2005)
56EEAmeya R. Agnihotri, Satoshi Ono, Chen Li, Mehmet Can Yildiz, Ateen Khatkhate, Cheng-Kok Koh, Patrick H. Madden: Mixed block placement via fractional cut recursive bisection. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 748-761 (2005)
2004
55EERuibing Lu, Cheng-Kok Koh: A high performance bus communication architecture through bus splitting. ASP-DAC 2004: 751-755
54EEYiran Chen, Kaushik Roy, Cheng-Kok Koh: Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. ASP-DAC 2004: 893-898
53EENgai Wong, Venkataramanan Balakrishnan, Cheng-Kok Koh: Passivity-preserving model reduction via a computationally efficient project-and-balance scheme. DAC 2004: 369-374
52EEAiqun Cao, Cheng-Kok Koh: Post-layout logic optimization of domino circuits. DAC 2004: 820-825
51EEChen Li, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden: Routability-driven placement and white space allocation. ICCAD 2004: 394-401
50EEJitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan: Fast simulation of VLSI interconnects. ICCAD 2004: 93-98
49EEAteen Khatkhate, Chen Li, Ameya R. Agnihotri, Mehmet Can Yildiz, Satoshi Ono, Cheng-Kok Koh, Patrick H. Madden: Recursive bisection based mixed block placement. ISPD 2004: 84-89
2003
48EEGuoan Zhong, Cheng-Kok Koh, Venkataramanan Balakrishnan, Kaushik Roy: An adaptive window-based susceptance extraction and its efficient implementation. DAC 2003: 728-731
47EERuibing Lu, Cheng-Kok Koh: Interconnect Planning with Local Area Constrained Retiming. DATE 2003: 10442-10447
46EERuibing Lu, Cheng-Kok Koh: Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels. ICCAD 2003: 227-231
45EERuibing Lu, Cheng-Kok Koh: SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. ICCAD 2003: 8-12
44EEAiqun Cao, Cheng-Kok Koh: Non-Crossing OBDDs for Mapping to Regular Circuit Structures. ICCD 2003: 338-343
43EEYiran Chen, Kaushik Roy, Cheng-Kok Koh: Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. ISLPED 2003: 229-234
42EEWai-Ching Douglas Lam, Cheng-Kok Koh, Chung-Wen Albert Tsao: Clock Scheduling for Power Supply Noise Suppression using Genetic Algorithm with Selective Gene Therapy. ISQED 2003: 327-332
41EEGuoan Zhong, Cheng-Kok Koh, Kaushik Roy: On-chip interconnect modeling by wire duplication. IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1521-1532 (2003)
2002
40EEQ. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh: A factorization-based framework for passivity-preserving model reduction of RLC systems. DAC 2002: 40-45
39EERuibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao: Flip-Flop and Repeater Insertion for Early Interconnect Planning. DATE 2002: 690-695
38EEYiran Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Kaushik Roy: Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods. DATE 2002: 931-937
37EEGuoan Zhong, Cheng-Kok Koh, Kaushik Roy: On-chip interconnect modeling by wire duplication. ICCAD 2002: 341-346
36EEGuoan Zhong, Cheng-Kok Koh: Exact Closed Form Formula for Partial Mutual Inductances of On-Chip Interconnects. ICCD 2002: 428-433
35EEAiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy: Synthesis of Selectively Clocked Skewed Logic Circuits. ISQED 2002: 229-234
34EEWai-Ching Douglas Lam, Cheng-Kok Koh, Chung-Wen Albert Tsao: Power Supply Noise Suppression via Clock Skew Scheduling. ISQED 2002: 355-360
33EEQ. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh: Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods. VLSI Design 2002: 311-316
32EEShiyou Zhao, Kaushik Roy, Cheng-Kok Koh: Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. VLSI Design 2002: 489-
31EEChung-Wen Albert Tsao, Cheng-Kok Koh: UST/DME: a clock tree router for general skew constraints. ACM Trans. Design Autom. Electr. Syst. 7(3): 359-379 (2002)
30EEShiyou Zhao, Kaushik Roy, Cheng-Kok Koh: Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 81-92 (2002)
2001
29 Kaushik Roy, Sung-Mo Kang, Cheng-Kok Koh: Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001 ACM 2001
28EERongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes: Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration. DAC 2001: 846-851
27EEProbir Sarkar, Cheng-Kok Koh: Repeater block planning under simultaneous delay and transition time constraints. DATE 2001: 540-545
26EERongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes: Power trends and performance characterization of 3-dimensional integration. ISCAS (4) 2001: 414-417
25EERui Wang, Kaushik Roy, Cheng-Kok Koh: Short-circuit power analysis of an inverter driving an RLC load. ISCAS (4) 2001: 886-889
24EENaran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy: Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. ISLPED 2001: 267-270
23EEShiyou Zhao, Kaushik Roy, Cheng-Kok Koh: Decoupling capacitance allocation for power supply noise suppression. ISPD 2001: 66-71
22EERongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes: Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations. ISQED 2001: 217-222
21EEJason Cong, Cheng-Kok Koh, Patrick H. Madden: Interconnect layout optimization under higher order RLC model forMCM designs. IEEE Trans. on CAD of Integrated Circuits and Systems 20(12): 1455-1463 (2001)
20EEProbir Sarkar, Cheng-Kok Koh: Routability-driven repeater block planning for interconnect-centricfloorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 660-671 (2001)
19EEJason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan: Interconnect sizing and spacing with consideration of couplingcapacitance. IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1164-1169 (2001)
2000
18EECheng-Kok Koh, Patrick H. Madden: Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures. ACM Great Lakes Symposium on VLSI 2000: 47-52
17 Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes: Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits. ICCAD 2000: 208-213
16 Chung-Wen Albert Tsao, Cheng-Kok Koh: UST/DME: A Clock Tree Router for General Skew Constraints. ICCAD 2000: 400-405
15 Guoan Zhong, Cheng-Kok Koh, Kaushik Roy: A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise. ICCAD 2000: 406-411
14 Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh: Frequency Domain Analysis of Switching Noise on Power Supply Network. ICCAD 2000: 487-492
13EEAlexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar: Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. ICCD 2000: 241-246
12EEShiyou Zhao, Kaushik Roy, Cheng-Kok Koh: Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits. ICCD 2000: 65-72
11EEProbir Sarkar, Vivek Sundararaman, Cheng-Kok Koh: Routability-driven repeater block planning for interconnect-centric floorplanning. ISPD 2000: 186-191
1998
10EEJason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao: Bounded-skew clock and Steiner routing. ACM Trans. Design Autom. Electr. Syst. 3(3): 341-388 (1998)
1997
9EEJason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo: Interconnect design for deep submicron ICs. ICCAD 1997: 478-485
8EEJason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan: Global interconnect sizing and spacing with consideration of coupling capacitance. ICCAD 1997: 628-633
7EEJason Cong, Cheng-Kok Koh: Interconnect layout optimization under higher-order RLC model. ICCAD 1997: 713-720
1996
6EEJason Cong, Cheng-Kok Koh, Kwok-Shing Leung: Simultaneous buffer and wire sizing for performance and power optimization. ISLPED 1996: 271-276
5EEJason Cong, Lei He, Cheng-Kok Koh, Patrick H. Madden: Performance optimization of VLSI interconnect layout. Integration 21(1-2): 1-94 (1996)
1995
4EEJason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao: Bounded-skew clock and Steiner routing under Elmore delay. ICCAD 1995: 66-71
3 Jason Cong, Cheng-Kok Koh: Minimum-Cost Bounded-Skew Clock Routing. ISCAS 1995: 215-218
1994
2EEJason Cong, Cheng-Kok Koh: Simultaneous driver and wire sizing for performance and power optimization. ICCAD 1994: 206-212
1EEJason Cong, Cheng-Kok Koh: Simultaneous driver and wire sizing for performance and power optimization. IEEE Trans. VLSI Syst. 2(4): 408-425 (1994)

Coauthor Index

1Ameya R. Agnihotri [49] [56]
2Venkataramanan Balakrishnan [33] [38] [40] [48] [50] [53] [60] [63] [70] [71] [72] [77] [78] [81] [85] [86]
3Aiqun Cao [24] [35] [44] [52] [58] [65] [66] [69] [75]
4Stephen Cauley [72]
5Wenwen Chai [88]
6Kai-Yuan Chao [39] [83] [84]
7Yiran Chen [38] [43] [54] [57] [59] [60] [73] [78] [79] [80] [87]
8Jason Cong [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [19] [21] [51] [74]
9Shawn Davidson [24]
10Lei He [5] [8] [9] [19]
11Jitesh Jain [50] [72] [77] [81] [85]
12J. Jam [60]
13David B. Janes [17] [22] [26] [28]
14Dan Jiao [88]
15Andrew B. Kahng [4] [10]
16Sung-Mo Kang [29]
17Ateen Khatkhate [49] [56]
18Kei-Yong Khoo [9]
19Wai-Ching Douglas Lam [34] [42] [60] [62]
20Kuang-Yao Lee [83] [84]
21Kwok-Shing Leung [6]
22Hai Li [59] [73] [79] [80] [87]
23Hong Li [63] [70] [77] [78] [81] [85]
24Jing Li [79]
25Chen Li [49] [51] [56] [64] [69] [74] [76]
26Sung Kyu Lim [67]
27Ruibing Lu [39] [45] [46] [47] [55] [65] [66] [68] [69] [75]
28Patrick H. Madden [5] [18] [21] [49] [51] [56] [64] [74]
29Jacob R. Minz [67]
30Satoshi Ono [49] [56]
31David Z. Pan (David Zhigang Pan) [8] [9] [19]
32Kaushik Roy [12] [13] [14] [15] [17] [22] [23] [24] [25] [26] [28] [29] [30] [32] [35] [37] [38] [41] [43] [48] [54] [57] [58] [59] [73]
33Probir Sarkar [11] [20] [27]
34Naran Sirisantana [24] [35] [58]
35Alexandre Solomatnikov [13]
36Dinesh Somasekhar [13]
37Q. Su [33] [40]
38Vivek Sundararaman [11]
39Chung-Wen Albert Tsao [4] [10] [16] [31] [34] [42]
40Kalliopi Tsota [86]
41Rui Wang [25]
42Ruilin Wang [82]
43Ting-Chi Wang [83] [84]
44Ngai Wong [53]
45Weng-Fai Wong [61] [80] [87]
46Min Xie [51] [74]
47Ya-Chi Yang [71]
48Mehmet Can Yildiz [49] [56]
49Rongtian Zhang [17] [22] [26] [28]
50Shiyou Zhao [12] [14] [23] [30] [32]
51Guoan Zhong [15] [36] [37] [39] [41] [48] [63]
52Yongxin Zhu [61]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)