dblp.uni-trier.dewww.uni-trier.de

Jaewon Kim Vis

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeerX - CSB - MetaPress - Google - Bing - Yahoo

*1997
4EEJaewon Kim, Sung-Mo Kang: An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout Design. DAC 1997: 456-459
1996
3EEJaewon Kim, Sung-Mo Kang: A new triple-layer OTC channel router. IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1059-1070 (1996)
1995
2EEJaewon Kim, Sung-Mo Kang: A timing-driven data path layout synthesis with integer programming. ICCAD 1995: 716-719
1994
1 Jaewon Kim, Sung-Mo Kang, Sachin S. Sapatnekar: High Performance CMOS Macromodule Layout Synthesis. ISCAS 1994: 179-182

Coauthor Index

1Sung-Mo Kang [1] [2] [3] [4]
2Sachin S. Sapatnekar [1]

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)