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Kurt Keutzer Vis

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*2009
128EEKrste Asanovic, Rastislav Bodík, James Demmel, Tony Keaveny, Kurt Keutzer, John Kubiatowicz, Nelson Morgan, David A. Patterson, Koushik Sen, John Wawrzynek, David Wessel, Katherine A. Yelick: A view of the parallel computing landscape. Commun. ACM 52(10): 56-67 (2009)
2008
127EEBryan C. Catanzaro, Kurt Keutzer, Bor-Yiing Su: Parallelizing CAD: a timely research agenda for EDA. DAC 2008: 12-17
126EESachin S. Sapatnekar, Eshel Haritan, Kurt Keutzer, Anirudh Devgan, Desmond Kirkpatrick, Stephen Meier, Duaine Pryor, Tom Spyrou: Reinventing EDA with manycore processors. DAC 2008: 126-127
125EENadathur Satish, Kaushik Ravindran, Kurt Keutzer: Scheduling task dependence graphs with variable task execution times onto heterogeneous multiprocessors. EMSOFT 2008: 149-158
124EEJoel Phillips, Kurt Keutzer, Michael Wrinn: Architecting parallel programs. ICCAD 2008: 4
123EEBryan C. Catanzaro, Narayanan Sundaram, Kurt Keutzer: Fast support vector machine training and classification on graphics processors. ICML 2008: 104-111
122EEKurt Keutzer, Kaushik Ravindran: Technology Mapping. Encyclopedia of Algorithms 2008
121EEWen-mei Hwu, Kurt Keutzer, Timothy G. Mattson: The Concurrency Challenge. IEEE Design & Test of Computers 25(4): 312-320 (2008)
2007
120EEFrancine Bacchini, Greg Spirakis, Juan Antonio Carballo, Kurt Keutzer, Aart J. de Geus, Fu-Chieh Hsu, Kazu Yamada: Megatrends and EDA 2017. DAC 2007: 21-22
119EENadathur Satish, Kaushik Ravindran, Kurt Keutzer: A decomposition-based constraint optimization approach for statically scheduling task graphs with communication delays to multiprocessors. DATE 2007: 57-62
118EEJike Chong, Nadathur Satish, Bryan C. Catanzaro, Kaushik Ravindran, Kurt Keutzer: Efficient Parallelization of H.264 Decoding with Macro Block Level Scheduling. ICME 2007: 1874-1877
2005
117EEYujia Jin, Nadathur Satish, Kaushik Ravindran, Kurt Keutzer: An automated exploration framework for FPGA-based soft multiprocessor systems. CODES+ISSS 2005: 273-278
116EEScott J. Weber, Kurt Keutzer: Using minimal minterms to represent programmability. CODES+ISSS 2005: 63-68
115EEDavid G. Chinnery, Kurt Keutzer: Closing the power gap between ASIC and custom: an ASIC perspective. DAC 2005: 275-280
114EEYujia Jin, William Plishker, Kaushik Ravindran, Nadathur Satish, Kurt Keutzer: Soft multiprocessor systems for network applications (abstract only). FPGA 2005: 271
113 Kaushik Ravindran, Nadathur Satish, Yujia Jin, Kurt Keutzer: An FPGA-based Soft Multiprocessor System for IPv4 Packet Forwarding. FPL 2005: 487-492
112EEDavid G. Chinnery, Kurt Keutzer: Linear programming for sizing, Vth and Vdd assignment. ISLPED 2005: 149-154
2004
111EEScott J. Weber, Matthew W. Moskewicz, Matthias Gries, Christian Sauer, Kurt Keutzer: Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures. CODES+ISSS 2004: 18-23
110EERobert Dahlberg, Kurt Keutzer, R. Bingham, Aart J. de Geus, Walden C. Rhines: EDA: this is serious business. DAC 2004: 1
109EERichard Goldman, Kurt Keutzer, Clive Bittlestone, Ahsan Bootehsaz, Shekhar Y. Borkar, E. Chen, Louis Scheffer, Chandramouli Visweswariah: Is statistical timing statistically significant? DAC 2004: 498
108EEChristian Sauer, Matthias Gries, José Ignacio Gómez, Scott J. Weber, Kurt Keutzer: Developing a Flexible Interface for RapidIO, Hypertransport, and PCI-Express. PARELEC 2004: 129-134
107EENiraj Shah, William Plishker, Kaushik Ravindran, Kurt Keutzer: NP-Click: A Productive Software Development Approach for Network Processors. IEEE Micro 24(5): 45-54 (2004)
2003
106EEChidamber Kulkarni, Matthias Gries, Christian Sauer, Kurt Keutzer: Programming challenges in network processor deployment. CASES 2003: 178-187
105EEMatthias Gries, Chidamber Kulkarni, Christian Sauer, Kurt Keutzer: Comparing Analytical Modeling with Simulation for Network Processors: A Case Study. DATE 2003: 20256-20261
104EEMasayuki Ito, David G. Chinnery, Kurt Keutzer: Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition. ICCD 2003: 21-
103EEDavid Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery, Brandon Thompson, Kurt Keutzer: Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization. ISLPED 2003: 158-163
2002
102EEGary Smith, Daya Nadamuni, Sharad Malik, Rick Chapman, John Fogelin, Kurt Keutzer, Grant Martin, Brian Bailey: Unified tools for SoC embedded systems: mission critical, mission impossible or mission irrelevant? DAC 2002: 479
101EEMichael Orshansky, Kurt Keutzer: A general probabilistic framework for worst case timing analysis. DAC 2002: 556-561
100EEWei Qin, Subramanian Rajagopalan, Manish Vachharajani, Hangsheng Wang, Xinping Zhu, David I. August, Kurt Keutzer, Sharad Malik, Li-Shiuan Peh: Design Tools for Application Specific Embedded Processors. EMSOFT 2002: 319-333
99EEPinhong Chen, Yuji Kukimoto, Kurt Keutzer: Refining switching window by time slots for crosstalk noise calculation. ICCAD 2002: 583-586
98EEKurt Keutzer, Sharad Malik, A. Richard Newton: From ASIC to ASIP: The Next Design Discontinuity. ICCD 2002: 84-90
97EEPinhong Chen, Yuji Kukimoto, Chin-Chi Teng, Kurt Keutzer: On convergence of switching windows computation in presence of crosstalk noise. ISPD 2002: 84-89
96EEKurt Keutzer, Michael Orshansky: From blind certainty to informed uncertainty. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 37-41
95EEFarhana Sheikh, Andreas Kuehlmann, Kurt Keutzer: Minimum-power retiming for dual-supply CMOS circuits. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 43-49
94EEAndrew Mihal, Chidamber Kulkarni, Matthew W. Moskewicz, Mel M. Tsai, Niraj Shah, Scott J. Weber, Yujia Jin, Kurt Keutzer, Christian Sauer, Kees A. Vissers, Sharad Malik: Developing Architectural Platforms: A Disciplined Approach. IEEE Design & Test of Computers 19(6): 6-16 (2002)
93EEMichael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu: Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 544-553 (2002)
2001
92EEPatrick Schaumont, Ingrid Verbauwhede, Kurt Keutzer, Majid Sarrafzadeh: A Quick Safari Through the Reconfiguration Jungle. DAC 2001: 172-177
91EEDavid G. Chinnery, Borivoje Nikolic, Kurt Keutzer: Achieving 550Mhz in an ASIC Methodology. DAC 2001: 420-425
90EEMarco Sgroi, Michael Sheets, Andrew Mihal, Kurt Keutzer, Sharad Malik, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli: Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design. DAC 2001: 667-672
89EEBret M. Victor, Kurt Keutzer: Bus Encoding to Prevent Crosstalk Delay. ICCAD 2001: 57-
88 Serdar Tasiran, Farzan Fallah, David G. Chinnery, Scott J. Weber, Kurt Keutzer: A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage. ICCD 2001: 82-88
87EEPinhong Chen, Kurt Keutzer, Desmond Kirkpatrick: Scripting for EDA Tools: A Case Study. ISQED 2001: 87-
86EESerdar Tasiran, Kurt Keutzer: Coverage Metrics for Functional Validation of Hardware Designs. IEEE Design & Test of Computers 18(4): 36-45 (2001)
85EEFarzan Fallah, Srinivas Devadas, Kurt Keutzer: OCCOM-efficient computation of observability-based code coveragemetrics for functional verification. IEEE Trans. on CAD of Integrated Circuits and Systems 20(8): 1003-1015 (2001)
84EEFarzan Fallah, Srinivas Devadas, Kurt Keutzer: Functional vector generation for HDL models using linearprogramming and Boolean satisfiability. IEEE Trans. on CAD of Integrated Circuits and Systems 20(8): 994-1002 (2001)
83EEMukul R. Prasad, Philip Chong, Kurt Keutzer: Why is Combinational ATPG Efficiently Solvable for Practical VLSI Circuits? J. Electronic Testing 17(6): 509-527 (2001)
2000
82EEDavid G. Chinnery, Kurt Keutzer: Closing the gap between ASIC and custom: an ASIC perspective. DAC 2000: 637-642
81 Pinhong Chen, Desmond Kirkpatrick, Kurt Keutzer: Switching Window Computation for Static Timing Analysis in Presence of Crosstalk Noise. ICCAD 2000: 331-337
80 Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu: Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. ICCAD 2000: 62-67
79 Pinhong Chen, Desmond Kirkpatrick, Kurt Keutzer: Miller Factor for Gate-Level Coupling Delay Calculation. ICCAD 2000: 68-74
78EEKurt Keutzer, A. Richard Newton, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli: System-level design: orthogonalization of concerns andplatform-based design. IEEE Trans. on CAD of Integrated Circuits and Systems 19(12): 1523-1543 (2000)
77EEDennis Sylvester, Kurt Keutzer: A global wiring paradigm for deep submicron design. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 242-252 (2000)
1999
76EEMukul R. Prasad, Philip Chong, Kurt Keutzer: Why is ATPG Easy? DAC 1999: 22-28
75EEKurt Keutzer, Kurt Wolf, David Pietromonaco, Jay Maxey, Jeff Lewis, Martin Lefebvre, Jeff Burns: Panel: Cell Libraries - Build vs. Buy; Static vs. Dynamic. DAC 1999: 341-342
74EERaul Camposano, Kurt Keutzer, Jerry Fiddler, Alberto L. Sangiovanni-Vincentelli, Jim Lansford: HW and SW in Embedded System Design: Loveboat, Shipwreck, or Ships Passing in the Night. DAC 1999: 76-77
73EEPinhong Chen, Kurt Keutzer: Towards true crosstalk noise analysis. ICCAD 1999: 132-138
72EEKurt Keutzer, A. Richard Newton: The MARCO/DARPA Gigascale Silicon Research Center. ICCD 1999: 14-
71EEDennis Sylvester, Kurt Keutzer: Getting to the bottom of deep submicron II: a global wiring paradigm. ISPD 1999: 193-200
70EEStan Y. Liao, Srinivas Devadas, Kurt Keutzer: A text-compression-based method for code size minimization in embedded systems. ACM Trans. Design Autom. Electr. Syst. 4(1): 12-38 (1999)
69 Dennis Sylvester, Kurt Keutzer: Rethinking Deep-Submicron Circuit Design. IEEE Computer 32(11): 25-33 (1999)
1998
68EEFarzan Fallah, Srinivas Devadas, Kurt Keutzer: OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification. DAC 1998: 152-157
67EEFarzan Fallah, Srinivas Devadas, Kurt Keutzer: Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability. DAC 1998: 528-533
66EEDennis Sylvester, Kurt Keutzer: Getting to the bottom of deep submicron. ICCAD 1998: 203-211
65EESrinivas Devadas, Kurt Keutzer: An algorithmic approach to optimizing fault coverage for BIST logic synthesis. ITC 1998: 164-
64EEStan Y. Liao, Kurt Keutzer, Steven W. K. Tjiang, Srinivas Devadas: A new viewpoint on code generation for directed acyclic graphs. ACM Trans. Design Autom. Electr. Syst. 3(1): 51-75 (1998)
63EEStan Y. Liao, Srinivas Devadas, Kurt Keutzer: Code density optimization for embedded DSP processors using data compression techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 17(7): 601-608 (1998)
1997
62EEKurt Keutzer: Challenges in CAD for the One Million Gate FPGA. FPGA 1997: 133-134
61EEKurt Keutzer, A. Richard Newton, Narendra V. Shenoy: The future of logic synthesis and physical design in deep-submicron process geometries. ISPD 1997: 218-224
60EEJosé C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer, Jacob K. White: Estimation of average switching activity in combinational logic circuits using symbolic simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 121-127 (1997)
1996
59 Kurt Keutzer: The Need for Formal Methods for Integrated Circuit Design. FMCAD 1996: 1-18
58EESrinivas Devadas, Abhijit Ghosh, Kurt Keutzer: An observability-based code coverage metric for functional simulation. ICCAD 1996: 418-425
57EEKurt Keutzer, Olivier Coudert, Ramsey W. Haddad: What is the state of the art in commercial EDA tools for low power? ISLPED 1996: 181-187
56EEKurt Keutzer, Sharad Malik: Register Transfer Level Synthesis: From Theory to Practice. VLSI Design 1996: 2
55EEAnantha Chandrakasan, Kurt Keutzer, A. Khandekar, S. L. Maskara, B. D. Pradhan, Mani B. Srivastava: Mobile Communications: Demands on VLSI Technology, Design and CAD. VLSI Design 1996: 432-436
54EEStan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert Wang: Storage Assignment to Decrease Code Size. ACM Trans. Program. Lang. Syst. 18(3): 235-253 (1996)
53EESrinivas Devadas, Kurt Keutzer: Addendum to "Synthesis of robust delay-fault testable circuits: Theory". IEEE Trans. on CAD of Integrated Circuits and Systems 15(4): 445-446 (1996)
1995
52 Massoud Pedram, Robert W. Brodersen, Kurt Keutzer: Proceedings of the 1995 International Symposium on Low Power Design 1995, Dana Point, California, USA, April 23-26, 1995 ACM 1995
51EEStan Y. Liao, Srinivas Devadas, Kurt Keutzer: Code density optimization for embedded DSP processors using data compression techniques. ARVLSI 1995: 272-285
50EEStan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert Wang: Code Optimization Techniques for Embedded DSP Microprocessors. DAC 1995: 599-604
49EEPeter Vanbekbergen, Albert Wang, Kurt Keutzer: A Design and Validation System for Asynchronous Circuits. DAC 1995: 725-730
48EEStan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang: Instruction selection using binate covering for code size optimization. ICCAD 1995: 393-399
47 Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert Wang: Storage Assignment to Decrease Code Size. PLDI 1995: 186-195
46EELuciano Lavagno, Kurt Keutzer, Alberto L. Sangiovanni-Vincentelli: Synthesis of hazard-free asynchronous circuits with bounded wire delays. IEEE Trans. on CAD of Integrated Circuits and Systems 14(1): 61-86 (1995)
45EEKurt Keutzer, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli: Synthesis for testability techniques for asynchronous circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1569-1577 (1995)
1994
44 Guido Araujo, Srinivas Devadas, Kurt Keutzer, Stan Y. Liao, Sharad Malik, Ashok Sudarsanam, Steven W. K. Tjiang, Albert Wang: Challenges in code generation for embedded processors. Code Generation for Embedded Processors 1994: 48-64
43EEKurt Keutzer: Hardware-Software Co-Design and ESDA. DAC 1994: 435-436
42EESrinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Certified timing verification and the transition delay of a logic circuit. IEEE Trans. VLSI Syst. 2(3): 333-342 (1994)
41EESrinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Event suppression: improving the efficiency of timing simulation for synchronous digital circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 13(6): 814-822 (1994)
40EESrinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Verification of asynchronous interface circuits with bounded wire delays. VLSI Signal Processing 7(1-2): 161-182 (1994)
1993
39EEKurt Keutzer: What is the Next Big Productivity Boost for Designers? (Panel Abstract). DAC 1993: 141
38 Pranav Ashar, Srinivas Devadas, Kurt Keutzer: Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks. Formal Methods in System Design 2(1): 93-112 (1993)
37EEHorng-Fei Jyu, Sharad Malik, Srinivas Devadas, Kurt Keutzer: Statistical timing analysis of combinational logic circuits. IEEE Trans. VLSI Syst. 1(2): 126-137 (1993)
36EESrinivas Devadas, Kurt Keutzer, Sharad Malik: Computation of floating mode delay in combinational circuits: theory and algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1913-1923 (1993)
35EESrinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Computation of floating mode delay in combinational circuits: practice and implementation. IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1924-1936 (1993)
34EEKwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer: Delay-fault test generation and synthesis for testability under a standard scan design methodology. IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1217-1231 (1993)
33EESrinivas Devadas, Kurt Keutzer, Sharad Malik: A synthesis-based test generation and compaction algorithm for multifaults. J. Electronic Testing 4(1): 91-104 (1993)
1992
32EEAbhijit Ghosh, Srinivas Devadas, Kurt Keutzer, Jacob White: Estimation of Average Switching Activity in Combinational and Sequential Circuits. DAC 1992: 253-259
31EESrinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Certified Timing Verification and the Transition Delay of a Logic Circuit. DAC 1992: 549-555
30EESrinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Verification of asynchronous interface circuits with bounded wire delays. ICCAD 1992: 188-195
29EEAmelia Shen, Abhijit Ghosh, Srinivas Devadas, Kurt Keutzer: On average power dissipation and random pattern testability of CMOS combinational logic networks. ICCAD 1992: 402-407
28 Srinivas Devadas, Horng-Fei Jyu, Kurt Keutzer, Sharad Malik: Statistical Timing Analysis of Combinational Circuits. ICCD 1992: 38-43
27EESrinivas Devadas, Kurt Keutzer: Synthesis of robust delay-fault-testable circuits: theory. IEEE Trans. on CAD of Integrated Circuits and Systems 11(1): 87-101 (1992)
26EESrinivas Devadas, Kurt Keutzer: Validatable nonrobust delay-fault testable circuits via logic synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 11(12): 1559-1573 (1992)
25EESrinivas Devadas, Kurt Keutzer: Synthesis of robust delay-fault-testable circuits: practice. IEEE Trans. on CAD of Integrated Circuits and Systems 11(3): 277-300 (1992)
24EEGary D. Hachtel, Reily M. Jacoby, Kurt Keutzer, Christopher R. Morrison: On properties of algebraic transformations and the synthesis of multifault-irredundant circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 11(3): 313-321 (1992)
23EESrinivas Devadas, Kurt Keutzer, Jacob K. White: Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation. IEEE Trans. on CAD of Integrated Circuits and Systems 11(3): 373-383 (1992)
22EEMichael J. Bryan, Srinivas Devadas, Kurt Keutzer: Necessary and sufficient conditions for hazard-free robust transistor stuck-open-fault testability in multilevel networks. IEEE Trans. on CAD of Integrated Circuits and Systems 11(6): 800-803 (1992)
1991
21EELuciano Lavagno, Kurt Keutzer, Alberto L. Sangiovanni-Vincentelli: Algorithms for Synthesis of Hazard-Free Asynchronous Circuits. DAC 1991: 302-308
20EESrinivas Devadas, Kurt Keutzer, Sharad Malik: A Synthesis-Based Test Generation and Compaction Algorithm for Multifaults. DAC 1991: 359-365
19EEKwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer: Robust Delay-Fault Test Generation and Synthesis for Testability Under A Standard Scan Design Methodology. DAC 1991: 80-86
18 Srinivas Devadas, Kurt Keutzer, Sharad Malik: Delay Computation in Combinational Logic Circuits: Theory and Algorithms. ICCAD 1991: 176-179
17 Kurt Keutzer, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli: Synthesis for Testability Techniques for Asynchronous Circuits. ICCAD 1991: 326-329
16 Srinivas Devadas, Kurt Keutzer, A. S. Krishnakumar: Design Verfication and Reachability Analysis Using Algebraic Manipulation. ICCD 1991: 250-258
15 Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer: A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits. ITC 1991: 403-410
14 Pranav Ashar, Srinivas Devadas, Kurt Keutzer: Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks. ITC 1991: 887-896
13 Kurt Keutzer: The Need for Formal Verification in Hardware Design and What Formal Verification Has Not Done for Me Lately. TPHOLs 1991: 77-86
12EESrinivas Devadas, Kurt Keutzer: A unified approach to the synthesis of fully testable sequential machines. IEEE Trans. on CAD of Integrated Circuits and Systems 10(1): 39-50 (1991)
11EEKurt Keutzer, Sharad Malik, Alexander Saldanha: Is redundancy necessary to reduce delay? IEEE Trans. on CAD of Integrated Circuits and Systems 10(4): 427-435 (1991)
1990
10EESrinivas Devadas, Kurt Keutzer: Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits. DAC 1990: 221-227
9EEKurt Keutzer, Sharad Malik, Alexander Saldanha: Is Redundancy Necessary to Reduce Delay. DAC 1990: 228-234
8 Kurt Keutzer: Impact and Evaluation of Competing Implementation Media for ASIC's (Panel Abstract). DAC 1990: 600
7 Srinivas Devadas, Kurt Keutzer: An Automata-Theoretic Approach to Behavioral Equivalence. ICCAD 1990: 30-33
6 Michael J. Bryan, Srinivas Devadas, Kurt Keutzer: Testability-Preserving Circuit Transformations. ICCAD 1990: 456-459
1989
5EEKurt Keutzer: Three Competing Design Methodologies for ASIC's: Architectual Synthesis, Logic Synthesis, Logic Synthesis and Module Generation. DAC 1989: 308-313
4EEWayne Wolf, Kurt Keutzer, Janaki Akella: Addendum to 'A kernel-finding state assignment algorithm for multi-level logic'. IEEE Trans. on CAD of Integrated Circuits and Systems 8(8): 925-927 (1989)
1988
3EEWayne Wolf, Kurt Keutzer, Janaki Akella: A Kernel-Finding State Assignment Algorithm for Multi-Level Logic. DAC 1988: 433-438
2 Kurt Keutzer, Wayne Wolf: Anatomy of a Hardware Compiler PLDI 1988: 95-104
1987
1EEKurt Keutzer: DAGON: Technology Binding and Local Optimization by DAG Matching. DAC 1987: 341-347

Coauthor Index

1Janaki Akella [3] [4]
2Guido Araujo [44]
3Krste Asanovic [128]
4Pranav Ashar [14] [38]
5David I. August [100]
6Francine Bacchini [120]
7Brian Bailey [102]
8R. Bingham [110]
9Clive Bittlestone [109]
10Rastislav Bodík [128]
11Ahsan Bootehsaz [109]
12Shekhar Y. Borkar (Shekhar Borkar) [109]
13Robert W. Brodersen [52]
14Michael J. Bryan [6] [22]
15Jeff Burns [75]
16Raul Camposano [74]
17Juan Antonio Carballo [120]
18Bryan C. Catanzaro [118] [123] [127]
19Anantha Chandrakasan (Anantha P. Chandrakasan) [55]
20Rick Chapman [102]
21E. Chen [109]
22Pinhong Chen [73] [79] [80] [81] [87] [93] [97] [99]
23Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng) [15] [19] [34]
24David G. Chinnery [82] [88] [91] [103] [104] [112] [115]
25Jike Chong [118]
26Philip Chong [76] [83]
27Olivier Coudert [57]
28Robert Dahlberg [110]
29Abhijit Davare [103]
30James Demmel [128]
31Srinivas Devadas [6] [7] [10] [12] [14] [15] [16] [18] [19] [20] [22] [23] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [40] [41] [42] [44] [47] [48] [50] [51] [53] [54] [58] [60] [63] [64] [65] [67] [68] [70] [84] [85]
32Anirudh Devgan [126]
33Farzan Fallah [67] [68] [84] [85] [88]
34Jerry Fiddler [74]
35John Fogelin [102]
36Aart J. de Geus [110] [120]
37Abhijit Ghosh [29] [32] [58] [60]
38Richard Goldman [109]
39José Ignacio Gómez [108]
40Matthias Gries [105] [106] [108] [111]
41Gary D. Hachtel [24]
42Ramsey W. Haddad [57]
43Eshel Haritan [126]
44Fu-Chieh Hsu [120]
45Chenming Hu [80] [93]
46Wen-mei Hwu [121]
47Masayuki Ito [104]
48Reily M. Jacoby [24]
49Yujia Jin [94] [113] [114] [117]
50Horng-Fei Jyu [28] [37]
51Tony Keaveny [128]
52A. Khandekar [55]
53Desmond Kirkpatrick [79] [81] [87] [126]
54A. S. Krishnakumar [16]
55John Kubiatowicz [128]
56Andreas Kuehlmann [95]
57Yuji Kukimoto [97] [99]
58Chidamber Kulkarni [94] [105] [106]
59Jim Lansford [74]
60Luciano Lavagno [17] [21] [45] [46]
61Martin Lefebvre [75]
62Jeff Lewis [75]
63Stan Y. Liao [44] [47] [48] [50] [51] [54] [63] [64] [70]
64Sharad Malik [9] [11] [18] [20] [28] [30] [31] [33] [35] [36] [37] [40] [41] [42] [44] [56] [90] [94] [98] [100] [102]
65Grant Martin [102]
66S. L. Maskara [55]
67Timothy G. Mattson [121]
68Jay Maxey [75]
69Stephen Meier [126]
70Andrew Mihal [90] [94]
71Linda S. Milor (Linda Milor) [80] [93]
72José C. Monteiro (José Monteiro) [60]
73Nelson Morgan [128]
74Christopher R. Morrison [24]
75Matthew W. Moskewicz [94] [111]
76Daya Nadamuni [102]
77A. Richard Newton [61] [72] [78] [98]
78David Nguyen [103]
79Borivoje Nikolic [91]
80Michael Orshansky [80] [93] [96] [101] [103]
81David A. Patterson [128]
82Massoud Pedram [52]
83Li-Shiuan Peh [100]
84Joel Phillips [124]
85David Pietromonaco [75]
86William Plishker [107] [114]
87B. D. Pradhan [55]
88Mukul R. Prasad [76] [83]
89Duaine Pryor [126]
90Wei Qin [100]
91Jan M. Rabaey [78] [90]
92Subramanian Rajagopalan [100]
93Kaushik Ravindran [107] [113] [114] [117] [118] [119] [122] [125]
94Walden C. Rhines [110]
95Alexander Saldanha [9] [11]
96Alberto L. Sangiovanni-Vincentelli [17] [21] [45] [46] [74] [78] [90]
97Sachin S. Sapatnekar [126]
98Majid Sarrafzadeh [92]
99Nadathur Satish [113] [114] [117] [118] [119] [125]
100Christian Sauer [94] [105] [106] [108] [111]
101Patrick Schaumont [92]
102Louis Scheffer [109]
103Koushik Sen [128]
104Marco Sgroi [90]
105Niraj Shah [94] [107]
106Michael Sheets [90]
107Farhana Sheikh [95]
108Amelia Shen [29]
109Narendra V. Shenoy [61]
110Gary Smith [102]
111Greg Spirakis [120]
112Tom Spyrou [126]
113Mani B. Srivastava [55]
114Bor-Yiing Su [127]
115Ashok Sudarsanam [44]
116Narayanan Sundaram [123]
117Dennis Sylvester [66] [69] [71] [77]
118Serdar Tasiran [86] [88]
119Chin-Chi Teng [97]
120Brandon Thompson [103]
121Steven W. K. Tjiang [44] [47] [48] [50] [54] [64]
122Mel M. Tsai [94]
123Manish Vachharajani [100]
124Peter Vanbekbergen [49]
125Ingrid Verbauwhede [92]
126Bret M. Victor [89]
127Kees A. Vissers [94]
128Chandramouli Visweswariah [109]
129Albert Wang [30] [31] [35] [40] [41] [42] [44] [47] [49] [50] [54]
130Hangsheng Wang [100]
131John Wawrzynek [128]
132Scott J. Weber [88] [94] [108] [111] [116]
133David Wessel [128]
134Jacob K. White (Jacob White) [23] [32] [60]
135Kurt Wolf [75]
136Wayne Wolf [2] [3] [4]
137Michael Wrinn [124]
138Kazu Yamada [120]
139Katherine A. Yelick [128]
140Xinping Zhu [100]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)