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Daher Kaiss Vis

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*2007
7EEDaher Kaiss, Marcelo Skaba, Ziyad Hanna, Zurab Khasidashvili: Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification. FMCAD 2007: 20-26
2006
6EEZurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna: Post-reboot Equivalence and Compositional Verification of Hardware. FMCAD 2006: 11-18
5EEDaher Kaiss, Silvian Goldenberg, Zurab Khasidashvili: Seqver : A Sequential Equivalence Verifier for Hardware Designs . ICCD 2006
4EENachum Dershowitz, Jieh Hsiang, Guan-Shieng Huang, Daher Kaiss: Boolean Rings for Intersection-Based Satisfiability. LPAR 2006: 482-496
2004
3EEZurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna: Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints. ICCAD 2004: 58-65
2EENachum Dershowitz, Jieh Hsiang, Guan-Shieng Huang, Daher Kaiss: Boolean Ring Satisfiability. SAT 2004
2001
1EEJohn Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss: CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. CAV 2001: 131-143

Coauthor Index

1Nachum Dershowitz [2] [4]
2Silvian Goldenberg [5]
3Ziyad Hanna [1] [3] [6] [7]
4Jieh Hsiang [2] [4]
5Guan-Shieng Huang [2] [4]
6Zurab Khasidashvili [3] [5] [6] [7]
7John Moondanos [1]
8Carl-Johan H. Seger [1]
9Marcelo Skaba [3] [6] [7]

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)