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D. N. Jayasimha Vis

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*2007
23EEJohn D. Owens, William J. Dally, Ron Ho, D. N. Jayasimha, Stephen W. Keckler, Li-Shiuan Peh: Research Challenges for On-Chip Interconnection Networks. IEEE Micro 27(5): 96-108 (2007)
2003
22EENachum Dershowitz, D. N. Jayasimha, Seungjoon Park: Bounded Fairness. Verification: Theory and Practice 2003: 304-317
21EED. N. Jayasimha, Loren Schwiebert, D. Manivannan, Jeff A. May: A foundation for designing deadlock-free routing algorithms in wormhole networks. J. ACM 50(2): 250-275 (2003)
2001
20EEN. S. Sundar, D. N. Jayasimha, Dhabaleswar K. Panda: Hybrid Algorithms for Complete Exchange in 2D Meshes. IEEE Trans. Parallel Distrib. Syst. 12(12): 1201-1218 (2001)
1997
19EEDavid R. Lutz, D. N. Jayasimha: The Half-Adder Form and Early Branch Condition Resolution. IEEE Symposium on Computer Arithmetic 1997: 266-273
18EED. N. Jayasimha, M. E. Hayder, S. K. Pillay: An Evaluation of Architectural Platforms for Parallel Navier-Stokes Computations. The Journal of Supercomputing 11(1): 41-60 (1997)
1996
17EEDavid R. Lutz, D. N. Jayasimha: Early Zero Detection. ICCD 1996: 545-
16EEN. S. Sundar, D. N. Jayasimha, Dhabaleswar K. Panda, P. Sadayappan: Hybrid Algorithms for Complete Exchange in 2D Meshes. International Conference on Supercomputing 1996: 181-188
15 Loren Schwiebert, D. N. Jayasimha: A Necessary and Sufficient Condition for Deadlock-Free Wormhole Routing. J. Parallel Distrib. Comput. 32(1): 103-117 (1996)
1995
14EED. N. Jayasimha, M. E. Hayder, S. K. Pillay: Parallelizing Navier-Stokes Computations on a Variety of Architectural Platforms. SC 1995
13EELoren Schwiebert, D. N. Jayasimha: A Universal Proof Technique for Deadlock-Free Routing in Interconnection Networks. SPAA 1995: 175-184
12 Loren Schwiebert, D. N. Jayasimha: Optimal Fully Adaptive Minimal Wormhole Routing for Meshes. J. Parallel Distrib. Comput. 27(1): 56-70 (1995)
11 David R. Lutz, D. N. Jayasimha: Do Fixed-Processor Communication-Time Tradeoffs Exist? Parallel Processing Letters 5: 311-320 (1995)
1994
10 D. N. Jayasimha: Fault Tolerance in a Multisensor Environment. SRDS 1994: 2-11
9 S. Sitharama Iyengar, D. N. Jayasimha, D. Nadig: A Versatile Architecture for the Distributed Sensor Integration Problem. IEEE Trans. Computers 43(2): 175-185 (1994)
1993
8 Jeff D. Martens, D. N. Jayasimha: Compiling for Hierarchical Shared Memory Multiprocessors. ICPP 1993: 107-110
7 Loren Schwiebert, D. N. Jayasimha: Mapping to Reduce Contention in Multiprocessor Architectures. IPPS 1993: 248-253
6EELoren Schwiebert, D. N. Jayasimha: Optimal fully adaptive wormhole routing for meshes. SC 1993: 782-791
1992
5 D. N. Jayasimha, Jeff D. Martens: Some Architectural and Compilation Issues in the Design of Hierarchical Shared-Memory Multiprocessors. IPPS 1992: 567-572
1991
4EEDavid R. Lutz, D. N. Jayasimha: What is an effective schedule? SPDP 1991: 158-161
1990
3 Jeff D. Martens, D. N. Jayasimha: A Tree Structured Hierarchical Memory Multiprocessor. ICPP (1) 1990: 561-562
1988
2 D. N. Jayasimha: Distributed Synchronizers. ICPP (1) 1988: 23-27
1987
1 D. N. Jayasimha: Parallel Access to Synchronization Variables. ICPP 1987: 97-100

Coauthor Index

1William J. Dally [23]
2Nachum Dershowitz [22]
3M. E. Hayder [14] [18]
4Ron Ho [23]
5S. Sitharama Iyengar [9]
6Stephen W. Keckler [23]
7David R. Lutz [4] [11] [17] [19]
8D. Manivannan [21]
9Jeff D. Martens [3] [5] [8]
10Jeff A. May [21]
11D. Nadig [9]
12John D. Owens [23]
13Dhabaleswar K. Panda [16] [20]
14Seungjoon Park [22]
15Li-Shiuan Peh [23]
16S. K. Pillay [14] [18]
17P. Sadayappan [16]
18Loren Schwiebert [6] [7] [12] [13] [15] [21]
19N. S. Sundar [16] [20]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)