Vikram Jandhyala Vis

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13EEArun V. Sathanur, Ritochit Chakraborty, Vikram Jandhyala: Accurate statistical analysis of a differential low noise amplifier using a combined SPICE-field solver approach. ISCAS 2008: 884-887
12EEArun V. Sathanur, Ritochit Chakraborty, Vikram Jandhyala: Statistical analysis of RF circuits using combined circuit simulator-full wave field solver approach. ICCAD 2007: 11-17
11EEDipanjan Gope, Albert E. Ruehli, Vikram Jandhyala: Speeding Up PEEC Partial Inductance Computations Using a QR-Based Algorithm. IEEE Trans. VLSI Syst. 15(1): 60-68 (2007)
10EEChuanyi Yang, Swagato Chakraborty, Dipanjan Gope, Vikram Jandhyala: A parallel low-rank multilevel matrix compression algorithm for parasitic extraction of electrically large structures. DAC 2006: 1053-1056
9EEHao Gang Wang, Chi Hou Chan, Leung Tsang, Vikram Jandhyala: On sampling algorithms in multilevel QR factorization method for magnetoquasistatic analysis of integrated circuits over multilayered lossy substrates. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1777-1792 (2006)
8EEDipanjan Gope, Indranil Chowdhury, Vikram Jandhyala: DiMES: multilevel fast direct solver based on multipole expansions for parasitic extraction of massively coupled 3D microelectronic structures. DAC 2005: 159-162
7EEVikram Jandhyala, Yasuo Kuga, David J. Allstot, C.-J. Richard Shi: Bridging Circuits and Electromagnetics in a Curriculum Aimed at Microelectronic Analog and Microwave Simulation and Design. MSE 2005: 45-46
6EEIndranil Chowdhury, Vikram Jandhyala: Multilevel multipole and local operators for potentials of the form r-lambda. Appl. Math. Lett. 18(10): 1184-1189 (2005)
5EEDipanjan Gope, Swagato Chakraborty, Vikram Jandhyala: A fast parasitic extractor based on low-rank multilevel matrix compression for conductor and dielectric modeling in microelectronics and MEMS. DAC 2004: 794-799
4EEPavel V. Nikitin, Vikram Jandhyala, Daniel White, Nathan Champagne, John D. Rockway, C.-J. Richard Shi, Chuanyi Yang, Yong Wang, Gong Ouyang, Rob Sharpe, John W. Rockway: Modeling and Simulation of Circuit-Electromagnetic Effects in Electronic Design Flow. ISQED 2004: 244-249
3EEDipanjan Gope, Vikram Jandhyala: Oct-tree-based multilevel low-rank decomposition algorithm for rapid 3-D parasitic extraction. IEEE Trans. on CAD of Integrated Circuits and Systems 23(11): 1575-1580 (2004)
2EEVikram Jandhyala, Yong Wang, Dipanjan Gope, C.-J. Richard Shi: Coupled Electromagnetic-Circuit Simulation of Arbitrarily-Shaped Conducting Structures Using Triangular Meshes. ISQED 2002: 38-42
1EEVikram Jandhyala, Scott Savage, J. Eric Bracken, Zoltan J. Cendes: Efficient Capacitance Computation for Structures with Non-Uniform Adaptive Surface Meshes. DAC 1999: 543-548

Coauthor Index

1David J. Allstot [7]
2J. Eric Bracken [1]
3Zoltan J. Cendes [1]
4Ritochit Chakraborty [12] [13]
5Swagato Chakraborty [5] [10]
6Nathan Champagne [4]
7Chi Hou Chan [9]
8Indranil Chowdhury [6] [8]
9Dipanjan Gope [2] [3] [5] [8] [10] [11]
10Yasuo Kuga [7]
11Pavel V. Nikitin [4]
12Gong Ouyang [4]
13John D. Rockway [4]
14John W. Rockway [4]
15Albert E. Ruehli [11]
16Arun V. Sathanur [12] [13]
17Scott Savage [1]
18Rob Sharpe [4]
19C.-J. Richard Shi [2] [4] [7]
20Leung Tsang [9]
21Hao Gang Wang [9]
22Yong Wang [2] [4]
23Daniel White [4]
24Chuanyi Yang [4] [10]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)