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Rajiv Jain Vis

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*2002
30EEAnil Nori, Rajiv Jain: Composite Applications: Process Based Application Development. TES 2002: 48-53
2001
29EEAnil Nori, Chandar Venkatraman, Rajiv Jain: Defining the Next Generation e-Business Platform: A Discussion of the Asers eBusiness Platform. IEEE Data Eng. Bull. 24(1): 18-22 (2001)
1997
28EER. K. Aditham, Rajiv Jain, Murali Srinivasan: Interest Based Collaboration Framework. WETICE 1997: 75-81
1996
27EEMinjoong Rim, Rajiv Jain: Valid Transformations: A New Class of Loop Transformations for High-Level Synthesis and Pipelined Scheduling Applications. IEEE Trans. Parallel Distrib. Syst. 7(4): 399-410 (1996)
26EEAshutosh Mujumdar, Rajiv Jain, Kewal K. Saluja: Incorporating performance and testability constraints during binding in high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1212-1225 (1996)
1995
25EEHao Zheng, Kewal K. Saluja, Rajiv Jain: Test application time reduction for scan based sequential circuits. Great Lakes Symposium on VLSI 1995: 188-191
24EEWing Hang Wong, Rajiv Jain: PARAS: system-level concurrent partitioning and scheduling. ICCAD 1995: 440-445
23EEMinjoong Rim, Yaw Fann, Rajiv Jain: Global scheduling with code-motions for high-level synthesis applications. IEEE Trans. VLSI Syst. 3(3): 379-392 (1995)
1994
22EEYaw Fann, Minjoong Rim, Rajiv Jain: Global Scheduling for High-Level Synthesis Applications. DAC 1994: 542-546
21 Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja: Behavioral Synthesis of Testable Designs. FTCS 1994: 436-445
20 Alok Sharma, Rajiv Jain: Register Estimation from Behavioral Specifications. ICCD 1994: 576-580
19 Minjoong Rim, Rajiv Jain: Valid Transformations: A New Class of Loop Transformations. ICPP 1994: 20-23
18 Minjoong Rim, Rajiv Jain: Estimating Performance Characteristics of Loop Transformations. ISCAS 1994: 249-252
17 Ashutosh Majumdar, Minjoong Rim, Rajiv Jain, Renato De Leone: BINET: An Algorithm for Solving the Binding Problem. VLSI Design 1994: 163-168
16EEMinjoong Rim, Ashutosh Mujumdar, Rajiv Jain, Renato De Leone: Optimal and heuristic algorithms for solving the binding problem. IEEE Trans. VLSI Syst. 2(2): 211-225 (1994)
15EEMinjoong Rim, Rajiv Jain: Lower-bound performance estimation for the high-level synthesis scheduling problem. IEEE Trans. on CAD of Integrated Circuits and Systems 13(4): 451-458 (1994)
14EEAshutosh Mujumdar, Rajiv Jain, Kewal K. Saluja: Incorporating testability considerations in high-level synthesis. J. Electronic Testing 5(1): 43-55 (1994)
1993
13EEAlok Sharma, Rajiv Jain: InSyn: Integrated Scheduling for DSP Applications. DAC 1993: 349-354
12EEAlok Sharma, Rajiv Jain: Estimating Architectural Resources and Performance for High-Level Synthesis Applications. DAC 1993: 355-360
1992
11EEMinjoong Rim, Rajiv Jain: Representing Conditional Branches for High-Level Synthesis Applications. DAC 1992: 106-111
10EEMinjoong Rim, Rajiv Jain, Renato De Leone: Optimal Allocation and Binding in High-Level Synthesis. DAC 1992: 120-123
9 Ashutosh Mujumdar, Kewal K. Saluja, Rajiv Jain: Incorporating Testability Considerations in High-Level Systhesis. FTCS 1992: 272-279
8 Minjoong Rim, Rajiv Jain: Estimating Lower-Bound Performance of Schedules Using a Relaxation Technique. ICCD 1992: 290-294
7EERajiv Jain, Alice C. Parker, Nohbyung Park: Predicting system-level area and delay for pipelined and nonpipelined designs. IEEE Trans. on CAD of Integrated Circuits and Systems 11(8): 955-965 (1992)
1991
6EERajiv Jain, Ashutosh Mujumdar, Alok Sharma, Hueymin Wang: Empirical Evaluation of Some High-Level Synthesis Scheduling Heuristics. DAC 1991: 686-689
1990
5 Rajiv Jain: MOSP: Module Selection for Pipelined Designs with Multi-Cycle Operations. ICCAD 1990: 212-215
1989
4EERajiv Jain, Kayhan Küçükçakar, Mitch J. Mlinar, Alice C. Parker: Experience with ADAM Synthesis System. DAC 1989: 56-61
1988
3EERajiv Jain, Alice C. Parker, Nohbyung Park: Module Selection for Pipelined Synthesis. DAC 1988: 542-547
2 Meera Balakrishnan, Rajiv Jain, C. S. Raghavendra: On Array Storage for Conflict-Free Memory Access for Parallel Processors. ICPP (1) 1988: 103-107
1987
1EERajiv Jain, Alice C. Parker, Nohbyung Park: Predicting Area-Time Tradeoffs for Pipelined Design. DAC 1987: 35-41

Coauthor Index

1R. K. Aditham [28]
2Meera Balakrishnan [2]
3Yaw Fann [22] [23]
4Kayhan Küçükçakar [4]
5Renato De Leone [10] [16] [17]
6Ashutosh Majumdar [17]
7Mitch J. Mlinar [4]
8Ashutosh Mujumdar [6] [9] [14] [16] [21] [26]
9Anil Nori [29] [30]
10Nohbyung Park [1] [3] [7]
11Alice C. Parker [1] [3] [4] [7]
12Cauligi S. Raghavendra (C. S. Raghavendra) [2]
13Minjoong Rim [8] [10] [11] [15] [16] [17] [18] [19] [22] [23] [27]
14Kewal K. Saluja [9] [14] [21] [25] [26]
15Alok Sharma [6] [12] [13] [20]
16Murali Srinivasan [28]
17Chandar Venkatraman [29]
18Hueymin Wang [6]
19Wing Hang Wong [24]
20Hao Zheng [25]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)