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James Jacob Vis

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*2000
16EEAnanta K. Majhi, V. D. Agrawak, James Jacob, Lalit M. Patnaik: Line coverage of path delay faults. IEEE Trans. VLSI Syst. 8(5): 610-614 (2000)
1998
15EEPramit Chavda, James Jacob, Vishwani D. Agrawal: Optimizing Logic Design Using Boolean Transforms. VLSI Design 1998: 218-221
14EEP. Srinivasa Rao, James Jacob: A Fast Two-level Logic Minimizer. VLSI Design 1998: 528-533
1997
13EEJames Jacob, P. Srinivas Sivakumar, Vishwani D. Agrawal: Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs. VLSI Design 1997: 514-515
1996
12EENripendra N. Biswas, C. Srikanth, James Jacob: Cubical CAMP for minimization of Boolean functions. VLSI Design 1996: 264-269
11EEAnanta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal: On test coverage of path delay faults. VLSI Design 1996: 418-421
10EEMandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal: Functional test generation for synchronous sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 15(7): 831-843 (1996)
1995
9EEAnanta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal: An efficient automatic test generation system for path delay faults in combinational circuits. VLSI Design 1995: 161-165
8EEJacob Augustine, Wen Feng, James Jacob: Logic minimization based approach for compressing image data. VLSI Design 1995: 225-228
7EEMandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal: Functional test generation for non-scan sequential circuits. VLSI Design 1995: 47-52
1994
6 P. R. Suresh Kumar, James Jacob, Mandyam-Komar Srinivas, Vishwani D. Agrawal: An Improved Deductive Fault Simulator. VLSI Design 1994: 307-310
1993
5 P. R. Suresh Kumar, Mandyam-Komar Srinivas, James Jacob: Efficient Technique to Reduce Gate Evaluations and Speed Up Fault Simulation. VLSI Design 1993: 104
1992
4 Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal: Finite State Machine Testing Based on Growth and Dissappearance Faults. FTCS 1992: 238-245
3EEJames Jacob, Vishwani D. Agrawal: Multiple fault detection in two-level multi-output circuits. J. Electronic Testing 3(2): 171-173 (1992)
1990
2 James Jacob, Nripendra N. Biswas: Further Comments on "Detection of Faults in Programmable Logic Arrays". IEEE Trans. Computers 39(1): 155-157 (1990)
1985
1 James Jacob, Nripendra N. Biswas: : A Testable PLA Design with Minimal Hardware and Test Set. ITC 1985: 583-588

Coauthor Index

1V. D. Agrawak [16]
2Vishwani D. Agrawal [3] [4] [6] [7] [9] [10] [11] [13] [15]
3Jacob Augustine [8]
4Nripendra N. Biswas [1] [2] [12]
5Pramit Chavda [15]
6Wen Feng [8]
7P. R. Suresh Kumar [5] [6]
8Ananta K. Majhi [9] [11] [16]
9Lalit M. Patnaik [9] [11] [16]
10P. Srinivasa Rao [14]
11P. Srinivas Sivakumar [13]
12C. Srikanth [12]
13Mandyam-Komar Srinivas [4] [5] [6] [7] [10]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)