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Edward J. Hughes Vis

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*1996
1EEJohn Y. Sayah, Rajesh Gupta, Deepak D. Sherlekar, Philip S. Honsinger, Jitendra M. Apte, S. Wayne Bollinger, Hai Hsia Chen, Sumit DasGupta, Edward P. Hsieh, Andrew D. Huber, Edward J. Hughes, Zahi M. Kurzum, Vasant B. Rao, Thepthai Tabtieng, Vigen Valijan, David Y. Yang: Design planning for high-performance ASICs. IBM Journal of Research and Development 40(4): 431-452 (1996)

Coauthor Index

1Jitendra M. Apte [1]
2S. Wayne Bollinger [1]
3Hai Hsia Chen [1]
4Sumit DasGupta [1]
5Rajesh K. Gupta (Rajesh Gupta) [1]
6Philip S. Honsinger [1]
7Edward P. Hsieh [1]
8Andrew D. Huber [1]
9Zahi M. Kurzum [1]
10Vasant B. Rao [1]
11John Y. Sayah [1]
12Deepak D. Sherlekar [1]
13Thepthai Tabtieng [1]
14Vigen Valijan [1]
15David Y. Yang [1]

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)