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Jiang Hu Vis

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*2009
105EEPratik J. Shah, Jiang Hu: Impact of lithography-friendly circuit layout. ACM Great Lakes Symposium on VLSI 2009: 385-388
104EEYifang Liu, Jiang Hu: GPU-based parallelization for fast circuit optimization. DAC 2009: 943-946
103EEWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu: A single layer zero skew clock routing in X architecture. Science in China Series F: Information Sciences 52(8): 1466-1475 (2009)
2008
102EEYanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian: Low power clock buffer planning methodology in F-D placement for large scale circuit design. ASP-DAC 2008: 370-375
101EESridhar Varadan, Janet Meiling Wang, Jiang Hu: Handling partial correlations in yield prediction. ASP-DAC 2008: 543-548
100EENimay Shah, Rupak Samanta, Ming Zhang, Jiang Hu, Duncan Walker: Built-In Proactive Tuning System for Circuit Aging Resilience. DFT 2008: 96-104
99EEYifang Liu, Rupesh S. Shelar, Jiang Hu: Delay-optimal simultaneous technology mapping and placement with applications to timing optimization. ICCAD 2008: 101-106
98EEWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu: Gate planning during placement for gated clock network. ICCD 2008: 128-133
97EEYifang Liu, Jiang Hu, Weiping Shi: Multi-scenario buffer insertion in multi-core processor designs. ISPD 2008: 15-22
96EERupak Samanta, Jiang Hu, Peng Li: Discrete buffer and wire sizing for link-based non-tree clock networks. ISPD 2008: 175-181
95EEWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu: Activity and register placement aware gated clock network design. ISPD 2008: 182-189
94EERupak Samanta, Ganesh Venkataraman, Nimay Shah, Jiang Hu: Elastic Timing Scheme for Energy-Efficient and Robust Performance. ISQED 2008: 537-542
93EEXiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jiang Hu: Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding. ISQED 2008: 627-632
92EEYifang Liu, Jiang Hu, Weiping Shi: Buffering Interconnect for Multicore Processor Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2183-2196 (2008)
91EECheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen: Power Grid Analysis and Optimization Using Algebraic Multigrid. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 738-751 (2008)
90EEUday Padmanabhan, Janet Meiling Wang, Jiang Hu: Robust Clock Tree Routing in the Presence of Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1385-1397 (2008)
89EEWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu: Low Power Gated Clock Tree Driven Placement. IEICE Transactions 91-A(2): 595-603 (2008)
88EEWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu: Zero skew clock routing in X-architecture based on an improved greedy matching algorithm. Integration 41(3): 426-438 (2008)
2007
87EEBao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh Venkataraman: A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield. ASP-DAC 2007: 24-31
86EEJiang Hu, Andi Winterboer, Clifford Nass, Johanna D. Moore, Rebecca Illowsky: Context & usability testing: user-modeled information presentation in easy and difficult driving conditions. CHI 2007: 1343-1346
85EEShiyan Hu, Mahesh Ketkar, Jiang Hu: Gate Sizing For Cell Library-Based Designs. DAC 2007: 847-852
84EEShiyan Hu, Jiang Hu: Unified adaptivity optimization of clock and logic signals. ICCAD 2007: 125-130
83EECheng Zhuo, Huafeng Zhang, Rupak Samanta, Jiang Hu, Kangsheng Chen: Modeling, optimization and control of rotary traveling-wave oscillator. ICCAD 2007: 476-480
82EEXiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu: Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding. ICCAD 2007: 627-631
81EEShiyan Hu, Jiang Hu: Pattern sensitive placement for manufacturability. ISPD 2007: 27-34
80EEZhanyuan Jiang, Shiyan Hu, Jiang Hu, Weiping Shi: An Efficient Algorithm for RLC Buffer Insertion. ISQED 2007: 171-175
79EEWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu: Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture. ISQED 2007: 299-304
78EEYang Liu, Tong Zhang, Jiang Hu: Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders. ISQED 2007: 749-754
77EEWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu: Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. ISVLSI 2007: 383-388
76EEGanesh Venkataraman, Jiang Hu: A Placement Methodology for Robust Clocking. VLSI Design 2007: 881-886
75EEShiyan Hu, Qiuyang Li, Jiang Hu, Peng Li: Utilizing Redundancy for Timing Critical Interconnect. IEEE Trans. VLSI Syst. 15(10): 1067-1080 (2007)
74EEKe Cao, Jiang Hu, Mosong Cheng: Wire Sizing and Spacing for Lithographic Printability and Timing Optimization. IEEE Trans. VLSI Syst. 15(12): 1332-1340 (2007)
73EEGanesh Venkataraman, Jiang Hu, Frank Liu: Integrated Placement and Skew Optimization for Rotary Clocking. IEEE Trans. VLSI Syst. 15(2): 149-158 (2007)
72EEShiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin-Ngai Sze: Fast Algorithms for Slew-Constrained Minimum Cost Buffering. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2009-2022 (2007)
71EEBor-Yiing Su, Yao-Wen Chang, Jiang Hu: An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 719-733 (2007)
70EEChin-Ngai Sze, Charles J. Alpert, Jiang Hu, Weiping Shi: Path-Based Buffer Insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1346-1355 (2007)
2006
69EEMike Brzozowski, Kendra Carattini, Scott R. Klemmer, Patrick Mihelich, Jiang Hu, Andrew Y. Ng: groupTime: preference based group scheduling. CHI 2006: 1047-1056
68EEJamie Pearson, Jiang Hu, Holly P. Branigan, Martin J. Pickering, Clifford Nass: Adaptive language behavior in HCI: how expectations and beliefs about a system affect users' word choice. CHI 2006: 1177-1180
67EEShiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze: Fast algorithms for slew constrained minimum cost buffering. DAC 2006: 308-313
66EEShiyan Hu, Qiuyang Li, Jiang Hu, Peng Li: Steiner network construction for timing critical nets. DAC 2006: 379-384
65EEKe Cao, Sorin Dobre, Jiang Hu: Standard cell characterization considering lithography induced variations. DAC 2006: 801-804
64EEGanesh Venkataraman, Jiang Hu, Frank Liu, Cliff C. N. Sze: Integrated placement and skew optimization for rotary clocking. DATE 2006: 756-761
63EEMin-Seok Kim, Jiang Hu: Associative skew clock routing for difficult instances. DATE 2006: 762-767
62EECheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen: Fast decap allocation based on algebraic multigrid. ICCAD 2006: 107-111
61EEZhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li, Weiping Shi: A new RLC buffer insertion algorithm. ICCAD 2006: 553-557
60EERupak Samanta, Ganesh Venkataraman, Jiang Hu: Clock buffer polarity assignment for power noise reduction. ICCAD 2006: 558-562
59EEGanesh Venkataraman, Zhuo Feng, Jiang Hu, Peng Li: Combinatorial algorithms for fast clock mesh optimization. ICCAD 2006: 563-567
58EEWeixiang Shen, Yici Cai, Jiang Hu, Xianlong Hong, Bing Lu: High performance clock routing in X-architecture. ISCAS 2006
57EEUday Padmanabhan, Janet Meiling Wang, Jiang Hu: Statistical clock tree routing for robustness to process variations. ISPD 2006: 149-156
56EEBor-Yiing Su, Yao-Wen Chang, Jiang Hu: An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles. ISPD 2006: 56-63
55EECheng Zhuo, Jiang Hu, Kangsheng Chen: An Improved AMG-based Method for Fast Power Grid Analysis. ISQED 2006: 290-295
54EEZhuo Feng, Peng Li, Jiang Hu: Efficient Model Update for General Link-Insertion Networks. ISQED 2006: 43-50
53EEYang Liu, Tong Zhang, Jiang Hu: Low Power Trellis Decoder with Overscaled Supply Voltage. SiPS 2006: 205-208
52EEDi Wu, Jiang Hu, Rabi N. Mahapatra: Antenna Avoidance in Layer Assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 734-738 (2006)
51EECharles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze: Accurate estimation of global buffer delay within a floorplan. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1140-1145 (2006)
50EEAnand Rajaram, Jiang Hu, Rabi N. Mahapatra: Reducing clock skew variability via crosslinks. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1176-1182 (2006)
49EEAnand Rajaram, Bing Lu, Jiang Hu, Rabi N. Mahapatra, Wei Guo: Analytical bound for unwanted clock skew due to wire width variation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1869-1876 (2006)
2005
48EEDi Wu, Jiang Hu, Min Zhao, Rabi N. Mahapatra: Timing driven track routing considering coupling capacitance. ASP-DAC 2005: 1156-1159
47EEZhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi: Making fast buffer insertion even faster via approximation techniques. ASP-DAC 2005: 13-18
46EEKe Cao, Puneet Dhawan, Jiang Hu: Library cell layout with Alt-PSM compliance and composability. ASP-DAC 2005: 216-219
45EEYongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu: Register placement for low power clock network. ASP-DAC 2005: 588-593
44EEGanesh Venkataraman, Cliff C. N. Sze, Jiang Hu: Skew scheduling and clock routing for improved tolerance to process variations. ASP-DAC 2005: 594-599
43EELiang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu: Clock network minimization methodology based on incremental placement. ASP-DAC 2005: 99-102
42EEYongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu: Navigating registers in placement for clock network minimization. DAC 2005: 176-181
41EECliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi: Path based buffer insertion. DAC 2005: 509-514
40 Di Wu, Ganesh Venkataraman, Jiang Hu, Quiyang Li, Rabi N. Mahapatra: DiCER: distributed and cost-effective redundancy for variation tolerance. ICCAD 2005: 393-397
39 Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert: Practical techniques to reduce skew and its variations in buffered clock networks. ICCAD 2005: 592-596
38EEQianYing Wang, Clifford Nass, Jiang Hu: Natural Language Query vs. Keyword Search: Effects of Task Complexity on Search Performance, Participant Perceptions, and Preferences. INTERACT 2005: 106-116
37EEJiang Hu, Mike Brzozowski: Preference-Based Group Scheduling. INTERACT 2005: 990-993
36EEDi Wu, Jiang Hu, Rabi N. Mahapatra: Coupling aware timing optimization and antenna avoidance in layer assignment. ISPD 2005: 20-27
35EEAnand Rajaram, David Z. Pan, Jiang Hu: Improved algorithms for link-based non-tree clock networks for skew variability reduction. ISPD 2005: 55-62
34 QianYing Wang, Jiang Hu, Clifford Nass: Natural Language Interface Put in Perspective: Interaction of Search Method and Task Complexity. NLUCS 2005: 3-12
33EERishi Chaturvedi, Jiang Hu: An efficient merging scheme for prescribed skew clock routing. IEEE Trans. VLSI Syst. 13(6): 750-754 (2005)
32EEYongqiang Lu, Chin-Ngai Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu: Navigating Register Placement for Low Power Clock Network Design. IEICE Transactions 88-A(12): 3405-3411 (2005)
2004
31EEDi Wu, Jiang Hu, Rabi N. Mahapatra, Min Zhao: Layer assignment for crosstalk risk minimization. ASP-DAC 2004: 159-162
30EECliff C. N. Sze, Jiang Hu, Charles J. Alpert: A place and route aware buffered Steiner tree construction. ASP-DAC 2004: 355-360
29EEAnand Rajaram, Jiang Hu, Rabi N. Mahapatra: Reducing clock skew variability via cross links. DAC 2004: 18-23
28EECharles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay: Fast and flexible buffer trees that navigate the physical layout environment. DAC 2004: 24-29
27EEV. Seth, Min Zhao, Jiang Hu: Exploiting level sensitive latches in wire pipelining. ICCAD 2004: 283-290
26EECharles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze: Accurate estimation of global buffer delay within a floorplan. ICCAD 2004: 706-711
25EERishi Chaturvedi, Jiang Hu: Buffered Clock Tree for High Quality IC Design. ISQED 2004: 381-386
24EECharles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay: Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 136-141 (2004)
23EEHaihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif: A methodology for the simultaneous design of supply and signal networks. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1614-1624 (2004)
22EECharles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze: Porosity-aware buffered Steiner tree construction. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 517-526 (2004)
2003
21EEAnand Rajaram, Bing Lu, Wei Guo, Rabi N. Mahapatra, Jiang Hu: Analytical Bound for Unwanted Clock Skew due to Wire Width Variation. ICCAD 2003: 401-407
20EERishi Chaturvedi, Jiang Hu: A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing. ICCD 2003: 282-
19EECharles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay: Porosity aware buffered steiner tree construction. ISPD 2003: 158-165
18EEBing Lu, Jiang Hu, Gary Ellis, Haihua Su: Process variation aware clock tree routing. ISPD 2003: 174-181
17EEJiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham: Buffer insertion with adaptive blockage avoidance. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 492-498 (2003)
16EECharles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia: A practical methodology for early buffer and wire resource allocation. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 573-583 (2003)
2002
15EEHaihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif: Congestion-driven codesign of power and signal networks. DAC 2002: 64-69
14EECharles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay: Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. ISPD 2002: 104-109
13EEJiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham: Buffer insertion with adaptive blockage avoidance. ISPD 2002: 92-97
12EEJiang Hu, Sachin S. Sapatnekar: A timing-constrained simultaneous global routing algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1025-1036 (2002)
2001
11EECharles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia: A Practical Methodology for Early Buffer and Wire Resource Allocation. DAC 2001: 189-194
10 Jiang Hu, Sachin S. Sapatnekar: Performance Driven Global Routing Through Gradual Refinement. ICCD 2001: 481-483
9EECharles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar: Steiner tree optimization for buffers. Blockages and bays. ISCAS (5) 2001: 399-402
8EECharles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia: Buffered Steiner trees for difficult instances. ISPD 2001: 4-9
7EECharles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar: Steiner tree optimization for buffers, blockages, and bays. IEEE Trans. on CAD of Integrated Circuits and Systems 20(4): 556-562 (2001)
6EEJiang Hu, Sachin S. Sapatnekar: A survey on multi-net global routing for integrated circuits. Integration 31(1): 1-49 (2001)
2000
5 Jiang Hu, Sachin S. Sapatnekar: A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets. ICCAD 2000: 99-103
4EEJiang Hu, Sachin S. Sapatnekar: Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model. IEEE Trans. on CAD of Integrated Circuits and Systems 19(4): 446-458 (2000)
1999
3EEJiang Hu, Sachin S. Sapatnekar: FAR-DS: Full-Plane AWE Routing with Driver Sizing. DAC 1999: 84-89
2EEJiang Hu, Sachin S. Sapatnekar: Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model. ISPD 1999: 133-138
1EEHuibo Hou, Jiang Hu, Sachin S. Sapatnekar: Non-Hanan routing. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 436-444 (1999)

Coauthor Index

1Charles J. Alpert [7] [8] [9] [11] [13] [14] [16] [17] [19] [22] [24] [26] [28] [30] [39] [41] [47] [51] [67] [70] [72]
2Jinian Bian [102]
3Holly P. Branigan [68]
4Mike Brzozowski [37] [69]
5Yici Cai [32] [42] [43] [45] [58] [77] [79] [88] [89] [95] [98] [102] [103]
6Ke Cao [46] [65] [74]
7Kendra Carattini [69]
8Yao-Wen Chang [56] [71]
9Rishi Chaturvedi [20] [25] [33]
10Kangsheng Chen [55] [62] [83] [91]
11Mosong Cheng [74]
12Chris C. N. Chu (Chris Chu, Chris Chong-Nuen Chu) [14] [24]
13Puneet Dhawan [46]
14Sorin Dobre [65]
15Gary Ellis [18]
16Zhuo Feng [54] [59]
17Gopal Gandham [7] [9] [13] [14] [17] [19] [22] [24]
18Wei Guo [21] [49]
19Xianlong Hong [32] [42] [43] [45] [58] [77] [79] [88] [89] [95] [98] [102] [103]
20Huibo Hou [1]
21Milos Hrkic [8] [14] [19] [22] [24] [28]
22Shiyan Hu [61] [66] [67] [72] [75] [80] [81] [84] [85]
23Liang Huang [32] [42] [43] [45]
24Rebecca Illowsky [86]
25Nikhil Jayakumar [39]
26Zhanyuan Jiang [61] [80]
27Andrew B. Kahng [8] [87]
28Shrirang K. Karandikar [67] [72]
29Chandramouli V. Kashyap [14] [24]
30Mahesh Ketkar [85]
31Sunil P. Khatri [39]
32Min-Seok Kim [63]
33Scott R. Klemmer [69]
34Peng Li [39] [54] [59] [66] [75] [82] [93] [96]
35Qiuyang Li [66] [75]
36Quiyang Li [40]
37Zhuo Li [47] [61] [67] [72]
38John Lillis [8]
39Bao Liu [8] [87]
40Frank Liu [64] [73]
41Yang Liu [53] [78]
42Yifang Liu [92] [97] [99] [104]
43Bing Lu [18] [21] [49] [58] [79] [88] [103]
44Yongqiang Lu [32] [42] [43] [45]
45Rabi N. Mahapatra [21] [29] [31] [36] [40] [48] [49] [50] [52]
46Patrick McGuinness [39]
47Patrick Mihelich [69]
48Johanna D. Moore [86]
49Clifford Nass [34] [38] [68] [86]
50Sani R. Nassif [15] [23]
51José Luis Neves [7] [9]
52Andrew Y. Ng [69]
53Uday Padmanabhan [57] [90]
54David Z. Pan (David Zhigang Pan) [35]
55Rajendran Panda [82] [93]
56Jamie Pearson [68]
57Martin J. Pickering [68]
58Stephen T. Quay [7] [8] [9] [13] [14] [17] [19] [22] [24] [28]
59Anand Rajaram [21] [29] [35] [39] [49] [50]
60Rupak Samanta [60] [83] [94] [96] [100]
61Sachin S. Sapatnekar [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [15] [16] [23] [26] [51]
62V. Seth [27]
63Nimay Shah [94] [100]
64Pratik J. Shah [105]
65Rupesh S. Shelar [99]
66Weixiang Shen [58] [77] [79] [88] [89] [95] [98] [103]
67Weiping Shi [41] [47] [61] [67] [70] [72] [80] [92] [97]
68Bor-Yiing Su [56] [71]
69Haihua Su [15] [18] [23]
70A. J. Sullivan [8]
71Chin-Ngai Sze [32] [70] [72]
72Cliff C. N. Sze (Chin Ngai Sze, Cliff N. Sze) [22] [26] [30] [41] [42] [44] [45] [47] [51] [64] [67]
73Sridhar Varadan [101]
74Ganesh Venkataraman [39] [40] [44] [59] [60] [64] [73] [76] [87] [94]
75Paul G. Villarrubia (Paul Villarrubia) [8] [11] [16]
76Duncan Walker [100]
77Janet Meiling Wang (Janet Meiling Wang Roveda) [57] [90] [101]
78QianYing Wang [34] [38]
79Yanfeng Wang [102]
80Andi Winterboer [86]
81Di Wu [31] [36] [40] [48] [52]
82Xu Xu [87]
83Xiaoji Ye [82] [93]
84Huafeng Zhang [83]
85Ming Zhang [100]
86Tong Zhang [53] [78]
87Min Zhao [27] [31] [48] [62] [82] [91] [93]
88Qiang Zhou [32] [42] [43] [45] [102]
89Cheng Zhuo [55] [62] [83] [91]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)