| 1999 |
|---|
| 10 | EE | Yatin Vasant Hoskote,
Timothy Kam,
Pei-Hsin Ho,
Xudong Zhao:
Coverage Estimation for Symbolic Model Checking.
DAC 1999: 300-305 |
| 1998 |
|---|
| 9 | | Dinos Moundanos,
Jacob A. Abraham,
Yatin Vasant Hoskote:
Abstraction Techniques for Validation Coverage Analysis and Test Generation.
IEEE Trans. Computers 47(1): 2-14 (1998) |
| 1997 |
|---|
| 8 | EE | Yatin Vasant Hoskote,
Jacob A. Abraham,
Donald S. Fussell,
John Moondanos:
Automatic verification of implementations of large circuits against HDL specifications.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 217-228 (1997) |
| 1996 |
|---|
| 7 | | Yirng-An Chen,
Edmund M. Clarke,
Pei-Hsin Ho,
Yatin Vasant Hoskote,
Timothy Kam,
Manpreet Khaira,
John W. O'Leary,
Xudong Zhao:
Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking.
FMCAD 1996: 19-33 |
| 6 | | Dinos Moundanos,
Jacob A. Abraham,
Yatin Vasant Hoskote:
A Unified Framework for Design Validation and Manufacturing Test.
ITC 1996: 875-884 |
| 1995 |
|---|
| 5 | EE | Yatin Vasant Hoskote,
Jacob A. Abraham,
Donald S. Fussell:
Automated verification of temporal properties specified as state machines in VHDL.
Great Lakes Symposium on VLSI 1995: 100-105 |
| 4 | EE | Yatin Vasant Hoskote,
Dinos Moundanos,
Jacob A. Abraham:
Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors.
ICCD 1995: 532-537 |
| 3 | EE | Ashok Balivada,
Yatin Vasant Hoskote,
Jacob A. Abraham:
Verification of transient response of linear analog circuits.
VTS 1995: 42-47 |
| 1994 |
|---|
| 2 | | Yatin Vasant Hoskote,
John Moondanos,
Jacob A. Abraham,
Donald S. Fussell:
Verification of Circuits Described in VHDL through Extraction of Design Intent.
VLSI Design 1994: 417-420 |
| 1992 |
|---|
| 1 | | V. S. S. Nair,
Yatin Vasant Hoskote,
Jacob A. Abraham:
Probabilistic Evaluation of On-Line Checks in Fault-Tolerant Multiprocessor Systems.
IEEE Trans. Computers 41(5): 532-541 (1992) |
