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Xianlong Hong Vis

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*2009
214EERuijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong: Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. ASP-DAC 2009: 161-166
213EEXin Li, Yuchun Ma, Xianlong Hong: A novel thermal optimization flow using incremental floorplanning for 3D ICs. ASP-DAC 2009: 347-352
212EEXiaoyi Wang, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Jacob Relles: An efficient decoupling capacitance optimization using piecewise polynomial models. DATE 2009: 1190-1195
211EEYuchun Ma, Xiang Qiu, Xiangqing He, Xianlong Hong: Incremental power optimization for multiple supply voltage design. ISQED 2009: 280-286
210EELiu Dawei, Qiang Zhou, Jinian Bian, Yici Cai, Xianlong Hong: Cell shifting aware of wirelength and overlap. ISQED 2009: 506-510
209EEXu He, Sheqin Dong, Yuchun Ma, Xianlong Hong: Simultaneous buffer and interlayer via planning for 3D floorplanning. ISQED 2009: 740-745
208EEShan Zeng, Wenjian Yu, Wanping Zhang, Jian Wang, Xianlong Hong, Chung-Kuan Cheng: Efficient power network analysis with complete inductive modeling. ISQED 2009: 770-775
207EEShenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong: Substrate Topological Routing for High-Density Packages. IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 207-216 (2009)
206EEShan Zeng, Wenjian Yu, Jin Shi, Xianlong Hong, Chung-Kuan Cheng: Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures. IEICE Transactions 92-A(6): 1476-1484 (2009)
205EEHaixia Yan, Qiang Zhou, Xianlong Hong: Thermal aware placement in 3D ICs using quadratic uniformity modeling approach. Integration 42(2): 175-180 (2009)
204EEQiang Zhou, Xin Zhao, Yici Cai, Xianlong Hong: An MTCMOS technology for low-power physical design. Integration 42(3): 340-345 (2009)
203EEWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu: A single layer zero skew clock routing in X architecture. Science in China Series F: Information Sciences 52(8): 1466-1475 (2009)
2008
202EELiangpeng Guo, Yici Cai, Qiang Zhou, Le Kang, Xianlong Hong: A novel performance driven power gating based on distributed sleep transistor network. ACM Great Lakes Symposium on VLSI 2008: 255-260
201EEXin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong: LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. ASP-DAC 2008: 209-212
200EEYanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian: Low power clock buffer planning methodology in F-D placement for large scale circuit design. ASP-DAC 2008: 370-375
199EEXiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong: Heuristic power/ground network and floorplan co-design method. ASP-DAC 2008: 617-622
198EEShuai Li, Jin Shi, Yici Cai, Xianlong Hong: Vertical via design techniques for multi-layered P/G networks. ASP-DAC 2008: 623-628
197EEJiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto: Symmetry constraint based on mismatch analysis for analog layout in SOI technology. ASP-DAC 2008: 772-775
196EEShenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong: Topological routing to maximize routability for package substrate. DAC 2008: 566-569
195EEXing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong: MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. FPL 2008: 559-562
194EEWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu: Gate planning during placement for gated clock network. ICCD 2008: 128-133
193EEWeixiang Shen, Yici Cai, Xianlong Hong: Leakage power optimization for clock network using dual-Vth technology. ISCAS 2008: 2769-2772
192EEWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu: Activity and register placement aware gated clock network design. ISPD 2008: 182-189
191EEHaixia Yan, Qiang Zhou, Xianlong Hong: Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm. ISQED 2008: 289-292
190EEYin Shen, Yici Cai, Qiang Zhou, Xianlong Hong: DFM Based Detailed Routing Algorithm for ECP and CMP. ISQED 2008: 357-360
189EEXiang Qiu, Yuchun Ma, Xiangqing He, Xianlong Hong: IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization. ISQED 2008: 873-876
188EEYibo Wang, Yici Cai, Xianlong Hong: A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation. ISVLSI 2008: 221-226
187EEYanming Jia, Yici Cai, Xianlong Hong: Full-chip routing system for reducing Cu CMP & ECP variation. SBCCI 2008: 10-15
186EENing Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong: Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method. IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 1996-2006 (2008)
185EEZhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Zhe Feng, Lei He, Xianlong Hong: Fashion: A Fast and Accurate Solution to Global Routing Problem. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 726-737 (2008)
184EEXiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong: Early Stage Power Supply Planning: A Heuristic Method for Codesign of Power/Ground Network and Floorplan. IEICE Transactions 91-A(12): 3443-3450 (2008)
183EEYanming Jia, Yici Cai, Xianlong Hong: Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model. IEICE Transactions 91-A(12): 3783-3792 (2008)
182EEWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu: Low Power Gated Clock Tree Driven Placement. IEICE Transactions 91-A(2): 595-603 (2008)
181EELiangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong: Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage. IEICE Transactions 91-A(8): 2084-2090 (2008)
180EEYici Cai, Jin Shi, Zhu Pan, Xianlong Hong, Sheldon X.-D. Tan: Large scale P/G grid transient simulation using hierarchical relaxed approach. Integration 41(1): 153-160 (2008)
179EETom Tong Jing, Yu Hu, Zhe Feng, Xianlong Hong, Xiaodong Hu, Guiying Yan: A full-scale solution to the rectilinear obstacle-avoiding Steiner problem. Integration 41(3): 413-425 (2008)
178EEWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu: Zero skew clock routing in X-architecture based on an improved greedy matching algorithm. Integration 41(3): 426-438 (2008)
177EEYici Cai, Qiang Zhou, Xianlong Hong, Rui Shi, Yang Wang: Application of optical proximity correction technology. Science in China Series F: Information Sciences 51(2): 213-224 (2008)
2007
176EEYanming Jia, Yici Cai, Xianlong Hong: Dummy fill aware buffer insertion during routing. ACM Great Lakes Symposium on VLSI 2007: 31-36
175EEXinjie Wei, Yici Cai, Xianlong Hong: Physical aware clock skew rescheduling. ACM Great Lakes Symposium on VLSI 2007: 473-476
174EEOu He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong: An effective buffer planning algorithm for IP based fixed-outline SOC placement. ACM Great Lakes Symposium on VLSI 2007: 564-569
173EEYue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong Hong: New timing and routability driven placement algorithms for FPGA synthesis. ACM Great Lakes Symposium on VLSI 2007: 570-575
172EEJiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong: Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation. ASP-DAC 2007: 191-196
171EEZhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, Xianlong Hong: DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. ASP-DAC 2007: 256-261
170EEYi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan, Le Kang: Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos. ASP-DAC 2007: 367-372
169EELiangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong: Logic and Layout Aware Voltage Island Generation for Low Power Design. ASP-DAC 2007: 666-671
168EELe Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan: Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach. ASP-DAC 2007: 751-756
167EEYuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou: Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. ASP-DAC 2007: 920-925
166EEJeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong: Statistical model order reduction for interconnect circuits considering spatial correlations. DATE 2007: 1508-1513
165EENing Mi, Sheldon X.-D. Tan, Pu Liu, Jian Cui, Yici Cai, Xianlong Hong: Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks. ICCAD 2007: 48-53
164EEPingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou: 3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. ICCAD 2007: 590-597
163EEXinjie Wei, Yici Cai, Xianlong Hong: Effective Acceleration of Iterative Slack Distribution Process. ISCAS 2007: 1077-1080
162EEYanfeng Wang, Qiang Zhou, Xianlong Hong, Yici Cai: Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building. ISCAS 2007: 2040-2043
161EELingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma: A Fast 3D-BSG Algorithm for 3D Packing Problem. ISCAS 2007: 2044-2047
160EEHaixia Yan, Zhuoyuan Li, Xianlong Hong, Qiang Zhou: Unified Quadratic Programming Approach For 3-D Mixed Mode Placement. ISCAS 2007: 3411-3414
159EEWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu: Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture. ISQED 2007: 299-304
158EEYici Cai, Bin Liu, Jin Shi, Qiang Zhou, Xianlong Hong: Power Delivery Aware Floorplanning for Voltage Island Designs. ISQED 2007: 350-355
157EEHongjie Bai, Sheqin Dong, Xianlong Hong: Congestion Driven Buffer Planning for X-Architecture. ISQED 2007: 835-840
156EELiu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong: Interconnect Power Optimization Based on Timing Analysis. ISVLSI 2007: 119-124
155EEHailong Yao, Yici Cai, Xianlong Hong: CMP-aware Maze Routing Algorithm for Yield Enhancement. ISVLSI 2007: 239-244
154EEWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu: Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. ISVLSI 2007: 383-388
153EEYaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma: An accurate and efficient probabilistic congestion estimation model in x architecture. SLIP 2007: 25-32
152EETom Tong Jing, Zhe Feng, Yu Hu, Xianlong Hong, Xiaodong Hu, Guiying Yan: lambda-OAT: lambda-Geometry Obstacle-Avoiding Tree Construction With O(nlog n) Complexity. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2073-2079 (2007)
151EEZhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng: Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 645-658 (2007)
150EEJin Shi, Yici Cai, Sheldon X.-D. Tan, Jeffrey Fan, Xianlong Hong: Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 680-692 (2007)
149EEYici Cai, Bin Liu, Qiang Zhou, Xianlong Hong: Voltage Island Generation in Cell Based Dual-Vdd Design. IEICE Transactions 90-A(1): 267-273 (2007)
148EEYibo Wang, Yici Cai, Xianlong Hong, Yi Zou: Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration. IEICE Transactions 90-A(5): 1028-1037 (2007)
147EEYongqiang Lu, Xianlong Hong, Qiang Zhou, Yici Cai, Jun Gu: An efficient quadratic placement based on search space traversing technology. Integration 40(3): 253-260 (2007)
146EEYaoguang Wei, Sheqin Dong, Xianlong Hong: APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement. Integration 40(4): 406-419 (2007)
145EEJeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong: Partitioning-based decoupling capacitor budgeting via sequence of linear programming. Integration 40(4): 516-524 (2007)
144EEQiang Zhou, Yici Cai, Duo Li, Xianlong Hong: A Yield-Driven Gridless Router. J. Comput. Sci. Technol. 22(5): 653-660 (2007)
2006
143EEXianlong Hong, Yici Cai, Hailong Yao, Duo Li: DFM-aware Routing for Yield Enhancement. APCCAS 2006: 1091-1094
142EEQiang Zhou, Yi Zou, Yici Cai, Xianlong Hong: Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials. APCCAS 2006: 1635-1638
141EELiu Yang, Sheqin Dong, Xianlong Hong, Yuchun Ma: A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints. APCCAS 2006: 792-795
140EEBin Liu, Yici Cai, Qiang Zhou, Xianlong Hong: Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs. ASP-DAC 2006: 582-587
139EEZhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hong, Xiaodong Hu, Guiying Yan: DraXRouter: global routing in X-Architecture with dynamic resource assignment. ASP-DAC 2006: 618-623
138EEYiyu Shi, Tong Jing, Lei He, Zhe Feng, Xianlong Hong: CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model. ASP-DAC 2006: 630-635
137EEDi Long, Xianlong Hong, Sheqin Dong: Signal-path driven partition and placement for analog circuit. ASP-DAC 2006: 694-699
136EEJin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong: Efficient early stage resonance estimation techniques for C4 package. ASP-DAC 2006: 826-831
135EEHailong Yao, Subarna Sinha, Charles Chiang, Xianlong Hong, Yici Cai: Efficient process-hotspot detection using range pattern matching. ICCAD 2006: 625-632
134EEXin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong: A novel low-power physical design methodology for MTCMOS. ISCAS 2006
133EELijuan Luo, Qiang Zhou, Yici Cai, Xianlong Hong, Yibo Wang: A novel technique integrating buffer insertion into timing driven placement. ISCAS 2006
132EEHongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen: Buffer planning based on block exchanging. ISCAS 2006
131EEHailong Yao, Yici Cai, Xianlong Hong: Congestion-driven W-shape multilevel full-chip routing framework. ISCAS 2006
130EESheqin Dong, Shuyi Zheng, Xianlong Hong: Floorplanning for 2.5-D system integration using multi-layer-BSG structure. ISCAS 2006
129EEWeixiang Shen, Yici Cai, Jiang Hu, Xianlong Hong, Bing Lu: High performance clock routing in X-architecture. ISCAS 2006
128EEShaojun Wei, Sheqin Dong, Xianlong Hong, Youliang Wu: On handling the fixed-outline constraints of floorplanning using less flexibility first principles. ISCAS 2006
127EEYibo Wang, Yici Cai, Xianlong Hong: Performance and power aware buffered tree construction. ISCAS 2006
126EEJin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong: High accurate pattern based precondition method for extremely large power/ground grid analysis. ISPD 2006: 108-113
125EEZhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng: Integrating dynamic thermal via planning with 3D floorplanning algorithm. ISPD 2006: 178-185
124EEZhe Feng, Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan: An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane. ISPD 2006: 48-55
123EEXinjie Wei, Yici Cai, Xianlong Hong: Clock Skew Scheduling Under Process Variations. ISQED 2006: 237-242
122EEJeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong: Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming. ISQED 2006: 272-277
121EESheqin Dong, Fan Guo, Jun Yuan, Rensheng Wang, Xianlong Hong: A Novel Tour Construction Heuristic for Traveling Salesman Problem Using LFF Principle. JCIS 2006
120EESheqin Dong, Rensheng Wang, Fan Guo, Jun Yuan, Xianlong Hong: Floorplanning by A Revised 3-D Corner Block List with sub-C+-tree. JCIS 2006
119EESheqin Dong, Fan Guo, Jun Yuan, Rensheng Wang, Xianlong Hong: Stochastic Local Search Using the Search Space Smoothing Meta-Heuristic: A Case Study. JCIS 2006
118EEZhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani: Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. ACM Trans. Design Autom. Electr. Syst. 11(2): 325-345 (2006)
117EEHang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong: Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2402-2412 (2006)
116EEJingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu: A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design. Integration 39(4): 457-473 (2006)
115EEYu Hu, Tong Jing, Zhe Feng, Xianlong Hong, Xiaodong Hu, Guiying Yan: ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm. J. Comput. Sci. Technol. 21(1): 147-152 (2006)
114EEYici Cai, Bin Liu, Yan Xiong, Qiang Zhou, Xianlong Hong: Priority-Based Routing Resource Assignment Considering Crosstalk. J. Comput. Sci. Technol. 21(6): 913-921 (2006)
113EEYuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu: General Floorplans with L/T-Shaped Blocks Using Corner Block List. J. Comput. Sci. Technol. 21(6): 922-926 (2006)
112EEZuying Luo, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Xiaoyi Wang, Zhu Pan, Jingjing Fu: Time-domain analysis methodology for large-scale RLC circuits and its applications. Science in China Series F: Information Sciences 49(5): 665-680 (2006)
111EEXinjie Wei, Yici Cai, Meng Zhao, Xianlong Hong: Legitimate Skew Clock Routing with Buffer Insertion. VLSI Signal Processing 42(2): 107-116 (2006)
2005
110EEHailong Yao, Yici Cai, Xianlong Hong, Qiang Zhou: Improved multilevel routing with redundant via placement for yield and reliability. ACM Great Lakes Symposium on VLSI 2005: 143-146
109EERong Liu, Sheqin Dong, Xianlong Hong: Fixed-outline floorplanning based on common subsequence. ACM Great Lakes Symposium on VLSI 2005: 156-159
108EEQinglang Luo, Xianlong Hong, Qiang Zhou, Yici Cai: A new algorithm for layout of dark field alternating phase shifting masks. ACM Great Lakes Symposium on VLSI 2005: 221-224
107EEXiren Wang, Wenjian Yu, Zeyi Wang, Xianlong Hong: An improved direct boundary element method for substrate coupling resistance extraction. ACM Great Lakes Symposium on VLSI 2005: 84-87
106EEYang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu, Xiaodong Hu, Guiying Yan: Via-Aware Global Routing for Good VLSI Manufacturability and High Yield. ASAP 2005: 198-203
105EEYin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan: The polygonal contraction heuristic for rectilinear Steiner tree construction. ASP-DAC 2005: 1-6
104EEYici Cai, Zhu Pan, Sheldon X.-D. Tan, Xianlong Hong, Wenting Hou, Lifeng Wu: Relaxed hierarchical power/ground grid analysis. ASP-DAC 2005: 1090-1093
103EERenshen Wang, Sheqin Dong, Xianlong Hong: An improved P-admissible floorplan representation based on Corner Block List. ASP-DAC 2005: 1115-1118
102EEJun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu: LFF algorithm for heterogeneous FPGA floorplanning. ASP-DAC 2005: 1123-1126
101EETong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, Xianlong Hong, Jinjun Xiong, Lei He: A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem. ASP-DAC 2005: 115-120
100EEYongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu: Register placement for low power clock network. ASP-DAC 2005: 588-593
99EEYu Hu, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, Guiying Yan: An-OARSMan: obstacle-avoiding routing tree construction with good length performance. ASP-DAC 2005: 7-12
98EEJingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan: VLSI on-chip power/ground network optimization considering decap leakage currents. ASP-DAC 2005: 735-738
97EEYi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan: Analysis of buffered hybrid structured clock networks. ASP-DAC 2005: 93-98
96EELiang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu: Clock network minimization methodology based on incremental placement. ASP-DAC 2005: 99-102
95EEHang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong: Partitioning-based approach to fast on-chip decap budgeting and minimization. DAC 2005: 170-175
94EEYongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu: Navigating registers in placement for clock network minimization. DAC 2005: 176-181
93EEHongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen: A New Buffer Planning Algorithm Based on Room Resizing. EUC 2005: 291-299
92EELijuan Luo, Qiang Zhou, Xianlong Hong, Hanbin Zhou: Multi-stage Detailed Placement Algorithm for Large-Scale Mixed-Mode Layout Design. ICCSA (4) 2005: 896-905
91EEYunfeng Wang, Jinian Bian, Xianlong Hong, Liu Yang, Qiang Zhou, Qiang Wu: A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design. ICESS 2005: 275-286
90EEYici Cai, Bin Liu, Xiong Yan, Qiang Zhou, Xianlong Hong: A Hybrid Genetic Algorithm and Application to the Crosstalk Aware Track Assignment Problem. ICNC (3) 2005: 181-184
89EEXinjie Wei, Yici Cai, Xianlong Hong: Zero skew clock routing with tree topology construction using simulated annealing method. ISCAS (1) 2005: 101-104
88EEYici Cai, Yibo Wang, Xianlong Hong: A global interconnect optimization algorithm under accurate delay model using solution space smoothing. ISCAS (1) 2005: 93-96
87EEYiqian Zhang, Xianlong Hong, Yici Cai: An efficient algorithm for buffered routing tree construction under fixed buffer locations with accurate delay models. ISCAS (1) 2005: 97-100
86EEZhe Zhou, Sheqin Dong, Xianlong Hong, Yuliang Wu, Yoji Kajitani: A new approach based on LFF for optimization of dynamic hardware reconfigurations. ISCAS (2) 2005: 1210-1213
85EEYuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng: Performance constrained floorplanning based on partial clustering [IC layout]. ISCAS (2) 2005: 1863-1866
84EEYici Cai, Bin Liu, Qiang Zhou, Xianlong Hong: Integrated routing resource assignment for RLC crosstalk minimization. ISCAS (2) 2005: 1871-1874
83EERong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani: Fixed-outline floorplanning with constraints through instance augmentation. ISCAS (2) 2005: 1883-1886
82EEJingyu Xu, Xianlong Hong, Tong Jing: Timing-driven global routing with efficient buffer insertion. ISCAS (3) 2005: 2449-2452
81EEDi Long, Xianlong Hong, Sheqin Dong: Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit. ISCAS (3) 2005: 2999-3002
80EEYunfeng Wang, Jinian Bian, Xianlong Hong: Interconnect delay optimization via high level re-synthesis after floorplanning. ISCAS (6) 2005: 5641-5644
79EESong Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng: VLSI block placement with alignment constraints based on corner block list. ISCAS (6) 2005: 6222-6225
78EEZhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani: A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. ISCAS (6) 2005: 6230-6233
77EEYuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng: Buffer Planning Algorithm Based on Partial Clustered Floorplanning. ISQED 2005: 213-219
76EEZhenyu Qi, Hang Li, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong: Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery. ISQED 2005: 542-547
75EEJingyu Xu, Xianlong Hong, Tong Jing, Yang Yang: Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design. ISQED 2005: 616-621
74EESong Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng: Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. ISQED 2005: 628-633
73EEYici Cai, Bin Liu, Qiang Zhou, Xianlong Hong: A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design. PATMOS 2005: 257-266
72EEJin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan: Efficient Simulation of Power/Ground Networks with Package and Vias. PATMOS 2005: 318-328
71EEYu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan: A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design. SAMOS 2005: 344-353
70EEYibo Wang, Yici Cai, Xianlong Hong: A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model. VLSI Design 2005: 91-96
69EEYuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu: Buffer planning as an Integral part of floorplanning with consideration of routing congestion. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 609-621 (2005)
68EEQi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang: Spanning graph-based nonrectilinear steiner tree algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1066-1075 (2005)
67EEJingyu Xu, Xianlong Hong, Tong Jing: Timing-Driven Global Routing with Efficient Buffer Insertion. IEICE Transactions 88-A(11): 3188-3195 (2005)
66EEYongqiang Lu, Chin-Ngai Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu: Navigating Register Placement for Low Power Clock Network Design. IEICE Transactions 88-A(12): 3405-3411 (2005)
65EEBin Liu, Yici Cai, Qiang Zhou, Xianlong Hong: Crosstalk and Congestion Driven Layer Assignment Algorithm. IEICE Transactions 88-A(6): 1565-1572 (2005)
64EEYi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan: A Fast Delay Computation for the Hybrid Structured Clock Network. IEICE Transactions 88-A(7): 1964-1970 (2005)
63EEYici Cai, Jin Shi, Zuying Luo, Xianlong Hong: Modeling and Analysis of Mesh Tree Hybrid Power/Ground Networks with Multiple Voltage Supply in Time Domain. J. Comput. Sci. Technol. 20(2): 224-230 (2005)
62EEHailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong: Crosstalk-Aware Routing Resource Assignment. J. Comput. Sci. Technol. 20(2): 231-236 (2005)
61EEYici Cai, Xin Zhao, Qiang Zhou, Xianlong Hong: Shielding Area Optimization Under the Solution of Interconnect Crosstalk. J. Comput. Sci. Technol. 20(6): 901-906 (2005)
2004
60EEJingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan: A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery. ASP-DAC 2004: 505-510
59EESong Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu: A buffer planning algorithm with congestion optimization. ASP-DAC 2004: 615-620
58EEYuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu: Buffer allocation algorithm with consideration of routing congestion. ASP-DAC 2004: 621-623
57EEJingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu: A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design. ASP-DAC 2004: 677-682
56EEQi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang: Efficient octilinear Steiner tree construction based on spanning graphs. ASP-DAC 2004: 687-690
55EEYi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan: A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network. ICCD 2004: 344-349
54 Weikun Guo, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong: Partial random walk for large linear network analysis. ISCAS (5) 2004: 173-177
53 Yang Wang, Yici Cai, Xianlong Hong, Qiang Zhou: Algorithm for yield driven correction of layout. ISCAS (5) 2004: 241-245
52 Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong, Lei He, Jinjun Xiong: Shielding area optimization under the solution of interconnect crosstalk. ISCAS (5) 2004: 297-300
51 Meng Zhao, Xinjie Wei, Yici Cai, Xianlong Hong: Quick and effective buffered legitimate skew clock routing. ISCAS (5) 2004: 337-340
50 Sheqin Dong, Zhong Yang, Xianlong Hong, Yuliang Wu: Module placement based on quadratic programming and rectangle packing using less flexibility first principle. ISCAS (5) 2004: 61-64
49 Ling Zhang, Tong Jing, Xianlong Hong, Jingyu Xu, Jinjun Xiong, Lei He: Performance and RLC crosstalk driven global routing. ISCAS (5) 2004: 65-68
48 Changqi Yang, Xianlong Hong, Hannah Honghua Yang, Qiang Zhou, Yici Cai, Yongqiang Lu: Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration. ISCAS (5) 2004: 81-84
47 Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong: Layer assignment algorithm for RLC crosstalk minimization. ISCAS (5) 2004: 85-88
46 Hailong Yao, Qiang Zhou, Xianlong Hong, Yici Cai: Crosstalk driven routing resource assignment. ISCAS (5) 2004: 89-92
45EEZhu Pan, Yici Cai, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong: Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling. ISQED 2004: 63-68
44EEJingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan: Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery. PATMOS 2004: 433-441
43EEYin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan: An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design. PATMOS 2004: 442-452
42EEYuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu: Stairway compaction using corner block list and its applications with rectilinear blocks. ACM Trans. Design Autom. Electr. Syst. 9(2): 199-211 (2004)
41EETong Jing, Xianlong Hong, Jingyu Xu, Haiyun Bao, Chung-Kuan Cheng, Jun Gu: UTACO: a unified timing and congestion optimization algorithm for standard cell global routing. IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 358-365 (2004)
40EEXiaohai Wu, Xianlong Hong, Yici Cai, Zuying Luo, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai: Area minimization of power distribution network using efficient nonlinear programming techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1086-1094 (2004)
39EEYongjun Xu, Zuying Luo, Xiaowei Li, Li-Jian Li, Xianlong Hong: Leakage Current Estimation of CMOS Circuit with Stack Effect. J. Comput. Sci. Technol. 19(5): 708-717 (2004)
38EESong Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu: Fast Evaluation of Bounded Slice-Line Grid. J. Comput. Sci. Technol. 19(6): 973-980 (2004)
2003
37EEYuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu: Dynamic global buffer planning optimization based on detail block locating and congestion analysis. DAC 2003: 806-811
36EEWenjian Yu, Zeyi Wang, Xianlong Hong: Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics. ICCD 2003: 58-63
35EESong Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu: Evaluating a bounded slice-line grid assignment in O(nlogn) time. ISCAS (4) 2003: 708-711
34EERui Liu, Sheqin Dong, Xianlong Hong, Di Long, Jun Gu: Algorithms for analog VLSI 2D stack generation and block merging. ISCAS (4) 2003: 716-719
33EEYongqiang Lu, Xianlong Hong, Wenting Hou, Weimin Wu, Yici Cai: Combining clustering and partitioning in quadratic placement. ISCAS (4) 2003: 720-723
32EEYuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu: Arbitrary convex and concave rectilinear block packing based on corner block list. ISCAS (5) 2003: 493-496
31EEYuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu: An integrated floorplanning with an efficient buffer planning algorithm. ISPD 2003: 136-142
30EEJingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu: An efficient hierarchical timing-driven Steiner tree algorithm for global routing. Integration 35(2): 69-84 (2003)
29EEWenting Hou, Xianlong Hong, Weimin Wu, Yici Cai: FaSa: A Fast and Stable Quadratic Placement Algorithm. J. Comput. Sci. Technol. 18(3): 318-324 (2003)
28EETong Jing, Xianlong Hong, Haiyun Bao, Jingyu Xu, Gu Jun: SSTT: Efficient Local Search for GSI Global Routing. J. Comput. Sci. Technol. 18(5): 632-640 (2003)
27EEXianlong Hong, Tong Jing, Jingyu Xu, Haiyun Bao, Gu Jun: CNB: A Critical-Network-Based Timing Optimization Method for Standard Cell Global Routing. J. Comput. Sci. Technol. 18(6): 732-738 (2003)
26EESheqin Dong, Xianlong Hong, Yuliang Wu, Jun Gu: Deterministic VLSI Block Placement Algorithm Using Less Flexibility First Principle. J. Comput. Sci. Technol. 18(6): 739-746 (2003)
2002
25EETong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Jun Gu: A novel and efficient timing-driven global router for standard cell layout design based on critical network concept. ISCAS (1) 2002: 165-168
24EEShuzhou Fang, Zeyi Wang, Xianlong Hong: A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI. VLSI Design 2002: 305-310
23EEYuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu: Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. VLSI Design 2002: 387-392
22EEJingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu: An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing. VLSI Design 2002: 473-478
21EESheqin Dong, Shuo Zhou, Xianlong Hong, Chung-Kuan Cheng, Jun Gu, Yici Cai: An Optimum Placement Search Algorithm Based on Extended Corner Block List. J. Comput. Sci. Technol. 17(6): 699-707 (2002)
2001
20EEYuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu: VLSI floorplanning with boundary constraints based on corner block list. ASP-DAC 2001: 509-514
19EESheqin Dong, Xianlong Hong, Youliang Wu, Yizhou Lin, Jun Gu: VLSI block placement using less flexibility first principles. ASP-DAC 2001: 601-604
18EEWenting Hou, Hong Yu, Xianlong Hong, Yici Cai, Weimin Wu, Jun Gu, William H. Kao: A new congestion-driven placement algorithm based on cell inflation. ASP-DAC 2001: 605-608
17EEYuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu: Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. DAC 2001: 770-775
16EEXiaohai Wu, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai: Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques. ICCAD 2001: 153-157
15EEYuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu: Floorplanning with abutment constraints based on corner block list. Integration 31(1): 65-77 (2001)
2000
14EEZhang Yan, Wang Baohua, Yici Cai, Xianlong Hong: Area routing oriented hierarchical corner stitching with partial bin. ASP-DAC 2000: 105-110
13EEHong Yu, Xianlong Hong, Yici Cai: MMP: a novel placement algorithm for combined macro block and standard cell layout design. ASP-DAC 2000: 271-276
12EEJiangchun Gu, Zeyi Wang, Xianlong Hong: Hierarchical computation of 3-D interconnect capacitance using direct boundary element method. ASP-DAC 2000: 447-452
11EEShuzhou Fang, Xiaobo Tang, Zeyi Wang, Xianlong Hong: A simplified hybrid method for calculating the frequency-dependent inductances of transmission lines with rectangular cross section. ASP-DAC 2000: 453-456
10 Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu: Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. ICCAD 2000: 8-12
1999
9EEXiaohai Wu, Changge Qiao, Xianlong Hong: Design and Optimization of Power/Ground Network for Cell-Based VLSIs with Macro Cells. ASP-DAC 1999: 21-
8EEHaiyun Bao, Xianlong Hong, Yici Cai: A New Global Routing Algorithm Independent Of Net Ordering. ASP-DAC 1999: 245-248
7EEGang Huang, Xianlong Hong, Changge Qiao, Yici Cai: A Timing-Driven Block Placer Based on Sequence Pair Model. ASP-DAC 1999: 249-252
6EEJinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue, Xianlong Hong: FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking. ASP-DAC 1999: 363-
5EEJinsong Hou, Zeyi Wang, Xianlong Hong: The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance. ASP-DAC 1999: 93-
1997
4EEXianlong Hong, Tianxiong Xue, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh: TIGER: an efficient timing-driven global router for gate array and standard cell layout design. IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1323-1331 (1997)
1993
3EEXianlong Hong, Tianxiong Xue, Ernest S. Kuh, Chung-Kuan Cheng, Jin Huang: Performance-Driven Steiner Tree Algorithm for Global Routing. DAC 1993: 177-181
2EEJin Huang, Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh: An Efficient Timing-Driven Global Routing Algorithm. DAC 1993: 596-600
1992
1EEXianlong Hong, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh: FARM: An Efficient Feed-Through Pin Assignment Algorithm. DAC 1992: 530-535

Coauthor Index

1Hongjie Bai [93] [132] [157]
2Haiyun Bao [8] [25] [27] [28] [41]
3Wang Baohua [14]
4Jinsong Bei [6]
5Jinian Bian [6] [78] [80] [91] [118] [125] [151] [174] [195] [200] [210]
6Yici Cai [7] [8] [10] [13] [14] [15] [16] [17] [18] [20] [21] [22] [23] [25] [29] [30] [31] [32] [33] [35] [37] [40] [42] [44] [45] [46] [47] [48] [51] [52] [53] [55] [58] [59] [60] [61] [62] [63] [64] [65] [66] [70] [72] [73] [76] [78] [84] [87] [88] [89] [90] [94] [95] [96] [97] [98] [100] [104] [108] [110] [111] [112] [114] [117] [122] [123] [126] [127] [129] [131] [133] [134] [135] [136] [140] [142] [143] [144] [145] [147] [148] [149] [150] [154] [155] [158] [159] [162] [163] [165] [166] [168] [169] [170] [173] [175] [176] [177] [178] [180] [181] [182] [183] [184] [186] [187] [188] [190] [192] [193] [194] [195] [198] [199] [200] [202] [203] [204] [210] [212] [214]
7Zhen Cao [139] [171] [185]
8Guoqiang Chen [196] [207]
9Juanjuan Chen [195]
10Song Chen [31] [32] [35] [37] [38] [58] [59] [69] [74] [77] [79] [85] [93] [132]
11Chung-Kuan Cheng [1] [2] [3] [4] [10] [15] [16] [17] [20] [21] [23] [31] [32] [35] [37] [38] [40] [41] [42] [58] [59] [69] [74] [77] [79] [85] [113] [125] [151] [206] [208]
12Charles Chiang [135]
13Jason Cong [167] [201]
14Jian Cui [165]
15Wayne Wei-Ming Dai [16] [40]
16Liu Dawei [210]
17Robert P. Dick [164]
18Sheqin Dong [10] [15] [17] [19] [20] [21] [23] [26] [31] [32] [34] [35] [37] [38] [42] [50] [58] [59] [69] [74] [77] [79] [81] [83] [85] [86] [93] [102] [103] [109] [113] [119] [120] [121] [128] [130] [132] [137] [141] [146] [153] [156] [157] [161] [167] [172] [174] [197] [201] [209]
19Robi Dutta [196] [207]
20Jeffrey Fan [117] [122] [145] [150] [166]
21Shuzhou Fang [11] [24]
22Zhe Feng [99] [115] [124] [138] [152] [179] [185]
23Jingjing Fu [44] [60] [98] [112]
24Satoshi Goto [197]
25Jiangchun Gu [10] [12]
26Jun Gu [10] [15] [16] [17] [18] [19] [20] [21] [22] [23] [25] [26] [30] [31] [32] [34] [35] [37] [38] [40] [41] [42] [57] [58] [59] [69] [113] [116] [147]
27Fan Guo [119] [120] [121]
28Liangpeng Guo [169] [181] [202]
29Weikun Guo [54]
30Lei He [49] [52] [101] [138] [171] [185] [196] [207]
31Ou He [174] [197]
32Xiangqing He [189] [211]
33Xu He [209]
34Jinsong Hou [5]
35Wenting Hou [18] [29] [33] [104]
36Jiang Hu [66] [94] [96] [100] [129] [154] [159] [178] [182] [192] [194] [200] [203]
37Xiao-Dong Hu (Xiaodong Hu) [43] [71] [99] [105] [106] [115] [124] [139] [152] [179]
38Yu Hu [71] [99] [106] [115] [124] [139] [152] [171] [179] [185]
39Gang Huang [7] [10]
40Jin Huang [1] [2] [3] [4]
41Liang Huang [66] [94] [96] [100]
42Yanming Jia [176] [183] [187]
43Tom Tong Jing [152] [179] [196] [207]
44Tong Jing [22] [25] [27] [28] [30] [41] [43] [49] [56] [57] [67] [68] [71] [75] [82] [99] [101] [105] [106] [115] [116] [124] [138] [139] [171] [185]
45Gu Jun [27] [28]
46Yoji Kajitani [83] [86]
47Le Kang [168] [170] [202]
48William H. Kao [18]
49Ernest S. Kuh [1] [2] [3] [4]
50Duo Li [143] [144]
51Hang Li [76] [95] [117]
52Hao Li [173]
53Hongxing Li [6]
54Li-Jian Li [39]
55Shuai Li [198]
56Xiaowei Li [39]
57Xin Li [201] [213]
58Zhuoyuan Li [78] [118] [125] [151] [160] [164] [167]
59Jinghong Liang [101]
60I-Fan Liao [122]
61Yizhou Lin [19]
62Bin Liu [47] [65] [73] [84] [90] [114] [140] [149] [158]
63Jiayi Liu [172] [197]
64Pu Liu [165]
65Rong Liu [83] [109]
66Rui Liu [34]
67Shenghua Liu [196] [207]
68Di Long [34] [81] [137] [172]
69Bing Lu [129] [159] [178] [203]
70Yongqiang Lu [33] [48] [66] [94] [96] [100] [147]
71Lijuan Luo [92] [133]
72Qinglang Luo [108]
73Zuying Luo [39] [40] [44] [45] [54] [60] [63] [98] [112]
74Yuchun Ma [15] [17] [20] [23] [31] [32] [35] [37] [38] [42] [58] [59] [69] [74] [77] [79] [85] [113] [141] [153] [156] [161] [164] [167] [172] [174] [189] [201] [209] [211] [213]
75Ning Mi [165] [166] [186] [214]
76Zhu Pan [44] [45] [60] [98] [104] [112] [180]
77Vijay Pitchumani [78] [118] [125] [151]
78Zhenyu Qi [76] [95] [117]
79Changge Qiao [7] [9]
80Xiang Qiu [189] [211]
81Glenn Reinman [167]
82Jacob Relles [212]
83Prashant Saxena [78]
84Li Shang [164]
85Ruijing Shen [214]
86Weixiang Shen [129] [154] [159] [178] [182] [192] [193] [194] [203]
87Yin Shen [190]
88Jin Shi [63] [72] [126] [136] [150] [158] [168] [180] [184] [198] [199] [206]
89Rui Shi [177]
90Yiyu Shi [138] [139]
91Subarna Sinha [135]
92Chin-Ngai Sze [66]
93Cliff C. N. Sze (Chin Ngai Sze, Cliff N. Sze) [94] [100]
94Sheldon X.-D. Tan (Xiang-Dong Tan) [44] [45] [54] [55] [60] [64] [72] [76] [95] [97] [98] [104] [112] [117] [122] [126] [136] [145] [150] [165] [166] [168] [170] [180] [186] [212] [214]
95Xiaobo Tang [11]
96Jian Wang [208]
97Renshen Wang [103]
98Rensheng Wang [119] [120] [121]
99Xiaoyi Wang [112] [184] [199] [212]
100Xiren Wang [107]
101Yanfeng Wang [162] [200]
102Yang Wang [53] [177]
103Yibo Wang [70] [88] [127] [133] [148] [188] [197]
104Yin Wang [43] [105]
105Yunfeng Wang [80] [91]
106Zeyi Wang [5] [11] [12] [24] [36] [107]
107Shaojun Wei [128]
108Xing Wei [195]
109Xinjie Wei [51] [89] [111] [123] [163] [175]
110Yaoguang Wei [146] [153]
111Lifeng Wu [76] [95] [104] [117]
112Qiang Wu [91]
113Weimin Wu [18] [29] [33]
114Xiaohai Wu [9] [16] [40]
115Youliang Wu [19] [128]
116Yuliang Wu [26] [50] [86] [102]
117Jinjun Xiong [49] [52] [101] [171] [185]
118Yan Xiong [114]
119Jingyu Xu [22] [25] [27] [28] [30] [41] [49] [57] [67] [75] [82] [101] [116]
120Yongjun Xu [39]
121Hongxi Xue [6]
122Tianxiong Xue [3] [4]
123Guiying Yan [43] [71] [99] [105] [106] [115] [124] [139] [152] [179]
124Haixia Yan [160] [191] [205]
125Xiong Yan [90]
126Zhang Yan [14]
127Changqi Yang [48]
128Hannah Honghua Yang (Honghua Yang) [48] [118] [125] [151]
129Hannal Yang [78]
130Liu Yang [91] [141] [156]
131Yang Yang [43] [56] [68] [75] [105] [106]
132Zhong Yang [50]
133Hailong Yao [46] [62] [110] [131] [135] [143] [155]
134Hong Yu [13] [18]
135Wenjian Yu [36] [107] [151] [206] [208]
136Jun Yuan [102] [119] [120] [121]
137Shan Zeng [125] [151] [206] [208]
138Ling Zhang [49] [57] [101] [116]
139Lingyi Zhang [161]
140Tianpei Zhang [196] [207]
141Wanping Zhang [208]
142Yiqian Zhang [87]
143Meng Zhao [51] [111]
144Xin Zhao [52] [61] [134] [204]
145Shuyi Zheng [130]
146Hai Zhou [56] [68] [164]
147Hanbin Zhou [92]
148Pingqiang Zhou [164]
149Qiang Zhou [46] [47] [48] [52] [53] [55] [61] [62] [64] [65] [66] [73] [78] [84] [90] [91] [92] [94] [96] [97] [100] [108] [110] [114] [118] [125] [133] [134] [140] [142] [144] [147] [149] [151] [158] [160] [162] [164] [167] [169] [170] [173] [177] [181] [190] [191] [195] [200] [202] [204] [205] [210]
150Shuo Zhou [21]
151Zhe Zhou [86]
152Qi Zhu [56] [68] [106]
153Yue Zhuo [173]
154Yi Zou [55] [64] [97] [142] [148] [168] [170]

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)