| * | 2009 |
|---|
| 99 | | Jörg Henkel,
Sri Parameswaran:
Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009
ACM 2009 |
| 98 | EE | Lars Bauer,
Muhammad Shafique,
Jörg Henkel:
MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators.
CODES+ISSS 2009: 335-342 |
| 97 | EE | Talal Bonny,
Jörg Henkel:
LICT: left-uncompressed instructions compression technique to improve the decoding performance of VLIW processors.
DAC 2009: 903-906 |
| 96 | EE | Muhammad Shafique,
Lars Bauer,
Jörg Henkel:
A parallel approach for high performance hardware design of intra prediction in H.264/AVC Video Codec.
DATE 2009: 1434-1439 |
| 95 | EE | Nabeel Iqbal,
Jörg Henkel:
Efficient constant-time entropy decoding for H.264.
DATE 2009: 1440-1445 |
| 94 | EE | Mohammad Abdullah Al Faruque,
Thomas Ebi,
Jörg Henkel:
Configurable links for runtime adaptive on-chip communication.
DATE 2009: 256-261 |
| 93 | EE | Lars Bauer,
Muhammad Shafique,
Jörg Henkel:
Cross-architectural design space exploration tool for reconfigurable processors.
DATE 2009: 958-963 |
| 92 | EE | Jörg Henkel,
Vijaykrishnan Narayanan,
Sri Parameswaran,
Roshan G. Ragel:
Security and Dependability of Embedded Systems: A Computer Architects' Perspective.
VLSI Design 2009: 30-32 |
| 2008 |
|---|
| 91 | | Vijaykrishnan Narayanan,
C. P. Ravikumar,
Jörg Henkel,
Ali Keshavarzi,
Vojin G. Oklobdzija,
Barry M. Pangrle:
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008
ACM 2008 |
| 90 | EE | Dominic Hillenbrand,
Jörg Henkel:
Block cache for embedded systems.
ASP-DAC 2008: 322-327 |
| 89 | EE | Lars Bauer,
Muhammad Shafique,
Jörg Henkel:
Run-time instruction set selection in a transmutable embedded processor.
DAC 2008: 56-61 |
| 88 | EE | Mohammad Abdullah Al Faruque,
Rudolf Krist,
Jörg Henkel:
ADAM: run-time agent-based distributed application mapping for on-chip communication.
DAC 2008: 760-765 |
| 87 | EE | Mohammad Abdullah Al Faruque,
Jörg Henkel:
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures.
DATE 2008: 1238-1243 |
| 86 | EE | Lars Bauer,
Muhammad Shafique,
Stephanie Kreutz,
Jörg Henkel:
Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set.
DATE 2008: 752-757 |
| 85 | EE | Talal Bonny,
Jörg Henkel:
Instruction Re-encoding Facilitating Dense Embedded Code.
DATE 2008: 770-775 |
| 84 | EE | Lars Bauer,
Muhammad Shafique,
Jörg Henkel:
A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor.
FPL 2008: 203-208 |
| 83 | EE | Mohammad Abdullah Al Faruque,
Thomas Ebi,
Jörg Henkel:
ROAdNoC: runtime observability for an adaptive network on chip architecture.
ICCAD 2008: 543-548 |
| 82 | EE | Talal Bonny,
Jörg Henkel:
FBT: filled buffer technique to reduce code size for VLIW processors.
ICCAD 2008: 549-554 |
| 81 | EE | Muhammad Shafique,
Lars Bauer,
Jörg Henkel:
3-tier dynamically adaptive power-aware motion estimator for h.264/AVC video encoding.
ISLPED 2008: 147-152 |
| 80 | EE | Dimitrios N. Serpanos,
Jörg Henkel:
Dependability and Security Will Change Embedded Computing.
IEEE Computer 41(1): 103-105 (2008) |
| 79 | EE | Lars Bauer,
Muhammad Shafique,
Jörg Henkel:
Efficient Resource Utilization for an Extensible Processor Through Dynamic Instruction Set Adaptation.
IEEE Trans. VLSI Syst. 16(10): 1295-1308 (2008) |
| 78 | EE | Talal Bonny,
Jörg Henkel:
Efficient Code Compression for Embedded Processors.
IEEE Trans. VLSI Syst. 16(12): 1696-1707 (2008) |
| 77 | EE | Diana Marculescu,
Jörg Henkel:
Guest Editorial Special Section on Low-Power Electronics and Design.
IEEE Trans. VLSI Syst. 16(6): 609-610 (2008) |
| 76 | EE | Mohammad Abdullah Al Faruque,
Jörg Henkel:
QoS-supported On-chip Communication for Multi-processors.
International Journal of Parallel Programming 36(1): 114-139 (2008) |
| 75 | EE | Praveen Kalla,
Xiaobo Sharon Hu,
Jörg Henkel:
A Flexible Framework for Communication Evaluation in SoC Design.
International Journal of Parallel Programming 36(5): 457-477 (2008) |
| 2007 |
|---|
| 74 | EE | Mohammad Abdullah Al Faruque,
Jörg Henkel:
Transaction Specific Virtual Channel Allocation in QoS Supported On-chip Communication.
ASAP 2007: 48-53 |
| 73 | EE | Talal Bonny,
Jörg Henkel:
Instruction Splitting for Efficient Code Compression.
DAC 2007: 646-651 |
| 72 | EE | Lars Bauer,
Muhammad Shafique,
Simon Kramer,
Jörg Henkel:
RISPP: Rotating Instruction Set Processing Platform.
DAC 2007: 791-796 |
| 71 | EE | Andhi Janapsatya,
Aleksandar Ignjatovic,
Sri Parameswaran,
Jörg Henkel:
Instruction trace compression for rapid instruction cache simulation.
DATE 2007: 803-808 |
| 70 | EE | Talal Bonny,
Jörg Henkel:
Efficient code density through look-up table compression.
DATE 2007: 809-814 |
| 69 | EE | Muhammad Shafique,
Lars Bauer,
Jörg Henkel:
An Optimized Application Architecture of the H.264 Video Encoder for Application Specific Platforms.
ESTImedia 2007: 119-124 |
| 68 | EE | Mohammad Abdullah Al Faruque,
Thomas Ebi,
Jörg Henkel:
Run-time adaptive on-chip communication scheme.
ICCAD 2007: 26-31 |
| 67 | EE | Lars Bauer,
Muhammad Shafique,
Dirk Teufel,
Jörg Henkel:
A Self-Adaptive Extensible Embedded Processor.
SASO 2007: 344-350 |
| 2006 |
|---|
| 66 | | Wolfgang Nebel,
Mircea R. Stan,
Anand Raghunathan,
Jörg Henkel,
Diana Marculescu:
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006
ACM 2006 |
| 65 | EE | Talal Bonny,
Jörg Henkel:
Using Lin-Kernighan algorithm for look-up table compression to improve code density.
ACM Great Lakes Symposium on VLSI 2006: 259-265 |
| 64 | | Jürgen Becker,
Kurt Brändle,
Uwe Brinkschulte,
Jörg Henkel,
Wolfgang Karl,
Thorsten Köster,
Michael Wenz,
Heinz Wörn:
Digital On-Demand Computing Organism for Real-Time Systems.
ARCS Workshops 2006: 230-245 |
| 63 | EE | Mohammad Abdullah Al Faruque,
Gereon Weiss,
Jörg Henkel:
Bounded arbitration algorithm for QoS-supported on-chip communication.
CODES+ISSS 2006: 76-81 |
| 62 | EE | Haris Lekatsas,
Jörg Henkel,
Venkata Jakkula,
Srimat T. Chakradhar:
Using Shiftable Content Addressable Memories to Double Memory Capacity on Embedded Systems.
VLSI Design 2006: 639-644 |
| 61 | EE | Jiang Xu,
Wayne Wolf,
Jörg Henkel,
Srimat T. Chakradhar:
A design methodology for application-specific networks-on-chip.
ACM Trans. Embedded Comput. Syst. 5(2): 263-280 (2006) |
| 60 | EE | Praveen Kalla,
Xiaobo Sharon Hu,
Jörg Henkel:
Distance-based recent use (DRU): an enhancement to instruction cache replacement policies for transition energy reduction.
IEEE Trans. VLSI Syst. 14(1): 69-80 (2006) |
| 2005 |
|---|
| 59 | EE | Newton Cheung,
Sri Parameswaran,
Jörg Henkel:
Battery-aware instruction generation for embedded processors.
ASP-DAC 2005: 553-556 |
| 58 | EE | Praveen Kalla,
Xiaobo Sharon Hu,
Jörg Henkel:
A flexible framework for communication evaluation in SoC design.
ASP-DAC 2005: 956-959 |
| 57 | EE | Jiang Xu,
Wayne Wolf,
Jörg Henkel,
Srimat T. Chakradhar:
H.264 HDTV Decoder Using Application-Specific Networks-On-Chip.
ICME 2005: 1508-1511 |
| 56 | EE | Jiang Xu,
Wayne Wolf,
Jörg Henkel,
Srimat T. Chakradhar:
A methodology for design, modeling, and analysis of networks-on-chip.
ISCAS (2) 2005: 1778-1781 |
| 55 | EE | Haris Lekatsas,
Jörg Henkel,
Venkata Jakkula,
Srimat T. Chakradhar:
A Unified Architecture for Adaptive Compression of Data and Code on Embedded Systems.
VLSI Design 2005: 117-123 |
| 54 | EE | Tiehan Lv,
Jiang Xu,
Wayne Wolf,
Burak Ozer,
Jörg Henkel,
Srimat T. Chakradhar:
A Methodology for Architectural Design of Multimedia Multiprocessor SoCs.
IEEE Design & Test of Computers 22(1): 18-26 (2005) |
| 53 | EE | Sri Parameswaran,
Jörg Henkel:
Instruction code mapping for performance increase and energy reduction in embedded computer systems.
IEEE Trans. VLSI Syst. 13(4): 498-502 (2005) |
| 52 | EE | Haris Lekatsas,
Jörg Henkel,
Wayne Wolf:
Approximate arithmetic coding for bus transition reduction in low power designs.
IEEE Trans. VLSI Syst. 13(6): 696-707 (2005) |
| 2004 |
|---|
| 51 | EE | Newton Cheung,
Sri Parameswaran,
Jörg Henkel,
Jeremy Chan:
MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor.
DATE 2004: 1020-1027 |
| 50 | EE | Radu Marculescu,
Massoud Pedram,
Jörg Henkel:
Distributed Multimedia System Design: A Holistic Perspective.
DATE 2004: 1342-1349 |
| 49 | EE | Jiang Xu,
Wayne Wolf,
Jörg Henkel,
Srimat T. Chakradhar,
Tiehan Lv:
A Case Study in Networks-on-Chip Design for Embedded Video.
DATE 2004: 770-777 |
| 48 | EE | Newton Cheung,
Sri Parameswaran,
Jörg Henkel:
A quantitative study and estimation models for extensible instructions in embedded processors.
ICCAD 2004: 183-189 |
| 47 | EE | Jörg Henkel,
Wayne Wolf,
Srimat T. Chakradhar:
On-chip networks: A scalable, communication-centric embedded system design paradigm.
VLSI Design 2004: 845- |
| 46 | EE | Haris Lekatsas,
Jörg Henkel,
Srimat T. Chakradhar,
Venkata Jakkula:
Cypress: Compression and Encryption of Data and Code for Embedded Multimedia Systems.
IEEE Design & Test of Computers 21(5): 406-415 (2004) |
| 2003 |
|---|
| 45 | EE | Haris Lekatsas,
Jörg Henkel,
Srimat T. Chakradhar,
Venkata Jakkula,
Murugan Sankaradass:
CoCo: a hardware/software platform for rapid prototyping of code compression technologies.
DAC 2003: 306-311 |
| 44 | EE | Tiehan Lv,
Jörg Henkel,
Haris Lekatsas,
Wayne Wolf:
Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses.
DATE 2003: 10542-10549 |
| 43 | EE | Newton Cheung,
Jörg Henkel,
Sri Parameswaran:
Rapid Configuration and Instruction Selection for an ASIP: A Case Study.
DATE 2003: 10802-10809 |
| 42 | EE | Newton Cheung,
Sri Parameswaran,
Jörg Henkel:
INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors.
ICCAD 2003: 291-298 |
| 41 | EE | Praveen Kalla,
Xiaobo Sharon Hu,
Jörg Henkel:
LRU-SEQ: A Novel Replacement Policy for Transition Energy Reduction in Instruction Caches.
ICCAD 2003: 518-522 |
| 40 | EE | Ramesh Chandra,
Preeti Ranjan Panda,
Jörg Henkel,
Sri Parameswaran,
Loganath Ramachandran:
Specification and Design of Multi-Million Gate SOCs.
VLSI Design 2003: 18-19 |
| 39 | EE | Jörg Henkel,
Xiaobo Hu,
Shuvra S. Bhattacharyya:
Guest Editors' Introduction: Taking on the Embedded System Design Challenge.
IEEE Computer 36(4): 35-37 (2003) |
| 38 | EE | Jörg Henkel:
Closing the SoC Design Gap.
IEEE Computer 36(9): 119-121 (2003) |
| 37 | EE | Tiehan Lv,
Jörg Henkel,
Haris Lekatsas,
Wayne Wolf:
A dictionary-based en/decoding scheme for low-power data buses.
IEEE Trans. VLSI Syst. 11(5): 943-951 (2003) |
| 2002 |
|---|
| 36 | | Jörg Henkel,
Xiaobo Sharon Hu,
Rajesh Gupta,
Sri Parameswaran:
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, CODES 2002, Estes Park, Colorado, USA, May 6-8, 2002
ACM 2002 |
| 35 | EE | Haris Lekatsas,
Jörg Henkel,
Venkata Jakkula:
Design of an one-cycle decompression hardware for performance increase in embedded systems.
DAC 2002: 34-39 |
| 34 | EE | Tiehan Lv,
Wayne Wolf,
Jörg Henkel,
Haris Lekatsas:
An Adaptive Dictionary Encoding Scheme for SOC Data Buses.
DATE 2002: 1059 |
| 33 | EE | Tin-Man Lee,
Wayne Wolf,
Jörg Henkel:
Dynamic Runtime Re-Scheduling Allowing Multiple Implementations of a Task for Platform-Based Designs.
DATE 2002: 296-301 |
| 32 | EE | Haris Lekatsas,
Jörg Henkel:
ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs.
VLSI Design 2002: 113-120 |
| 31 | EE | Tony Givargis,
Frank Vahid,
Jörg Henkel:
System-level exploration for Pareto-optimal configurations in parameterized system-on-a-chip.
IEEE Trans. VLSI Syst. 10(4): 416-422 (2002) |
| 30 | EE | Jörg Henkel,
Yanbing Li:
Avalanche: an environment for design space exploration and optimization of low-power embedded systems.
IEEE Trans. VLSI Syst. 10(4): 454-468 (2002) |
| 29 | EE | Tony Givargis,
Frank Vahid,
Jörg Henkel:
Instruction-based system-level power evaluation of system-on-a-chip peripheral cores.
IEEE Trans. VLSI Syst. 10(6): 856-863 (2002) |
| 2001 |
|---|
| 28 | | Jan Madsen,
Jörg Henkel,
Xiaobo Sharon Hu:
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, CODES 2001, Copenhagen, Denmark, 2001
ACM 2001 |
| 27 | EE | Tony Givargis,
Frank Vahid,
Jörg Henkel:
Trace-driven system-level power evaluation of system-on-a-chip peripheral cores.
ASP-DAC 2001: 306-312 |
| 26 | EE | Jörg Henkel,
Haris Lekatsas:
A2BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs.
DAC 2001: 744-749 |
| 25 | EE | Tony Givargis,
Frank Vahid,
Jörg Henkel:
System-Level Exploration for Pareto-Optimal Configurations in Parameterized Systems-on-a-Chip.
ICCAD 2001: 25-30 |
| 24 | EE | Sri Parameswaran,
Jörg Henkel:
I-CoPES: Fast Instruction Code Placement for Embedded Systems to Improve Performance and Energy Efficiency.
ICCAD 2001: 635- |
| 23 | | Haris Lekatsas,
Jörg Henkel,
Wayne Wolf:
Design and simulation of a pipelined decompression architecture for embedded systems.
ISSS 2001: 63-68 |
| 22 | EE | Jörg Henkel,
Rolf Ernst:
An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques.
IEEE Trans. VLSI Syst. 9(2): 273-289 (2001) |
| 21 | EE | T. D. Givargis,
Frank Vahid,
Jörg Henkel:
Evaluating power consumption of parameterized cache and bus architectures in system-on-a-chip designs.
IEEE Trans. VLSI Syst. 9(4): 500-508 (2001) |
| 2000 |
|---|
| 20 | EE | Tony Givargis,
Frank Vahid,
Jörg Henkel:
A hybrid approach for core-based system-level power modeling.
ASP-DAC 2000: 141-146 |
| 19 | EE | Haris Lekatsas,
Jörg Henkel,
Wayne Wolf:
Code compression as a variable in hardware/software co-design.
CODES 2000: 120-124 |
| 18 | EE | Haris Lekatsas,
Jörg Henkel,
Wayne Wolf:
Code compression for low power embedded system design.
DAC 2000: 294-299 |
| 17 | EE | Jörg Henkel,
Tony Givargis,
Frank Vahid:
Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design.
DATE 2000: 333- |
| 16 | EE | Haris Lekatsas,
Wayne Wolf,
Jörg Henkel:
Arithmetic Coding for Low Power Embedded System Design.
Data Compression Conference 2000: 430-439 |
| 15 | EE | Haris Lekatsas,
Jörg Henkel,
Wayne Wolf:
A Decompression Architecture for Low Power Embedded Systems.
ICCD 2000: 571-574 |
| 14 | EE | Tony Givargis,
Frank Vahid,
Jörg Henkel:
Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores.
ISSS 2000: 163-171 |
| 1999 |
|---|
| 13 | EE | Jörg Henkel:
A Low Power Hardware/Software Partitioning Approach for Core-Based Embedded Systems.
DAC 1999: 122-127 |
| 12 | EE | Jörg Henkel:
A Methodology for Minimizing Power Dissipation of Embedded Systems through Hardware/Software Partitioning.
Great Lakes Symposium on VLSI 1999: 86- |
| 11 | EE | Tony Givargis,
Jörg Henkel,
Frank Vahid:
Interface and cache power exploration for core-based embedded system design.
ICCAD 1999: 270-273 |
| 1998 |
|---|
| 10 | | Jörg Henkel,
Rolf Ernst:
High-Level Estimation Techniques for Usage in Hardware/Software Co-Design.
ASP-DAC 1998: 353-360 |
| 9 | EE | Jörg Henkel,
Yanbing Li:
Energy-conscious HW/SW-partitioning of embedded systems: a case study on an MPEG-2 encoder.
CODES 1998: 23-27 |
| 8 | EE | Yanbing Li,
Jörg Henkel:
A Framework for Estimation and Minimizing Energy Dissipation of Embedded HW/SW Systems.
DAC 1998: 188-193 |
| 1997 |
|---|
| 7 | EE | Jörg Henkel,
Rolf Ernst:
A Hardware/Software Partitioner Using a Dynamically Determined Granularity.
DAC 1997: 691-696 |
| 1996 |
|---|
| 6 | EE | Jörg Henkel,
Rolf Ernst:
The Interplay of Run-Time Estimation and Granularity in HW/SW Partitioning.
CODES 1996: 52-61 |
| 1995 |
|---|
| 5 | EE | Jörg Henkel,
Rolf Ernst:
A path-based technique for estimating hardware runtime in HW/SW-cosynthesis.
ISSS 1995: 116-121 |
| 1994 |
|---|
| 4 | EE | Dirk Herrmann,
Jörg Henkel,
Rolf Ernst:
An approach to the adaptation of estimated cost parameters in the COSYMA system.
CODES 1994: 100-107 |
| 3 | EE | Jörg Henkel,
Rolf Ernst,
Ulrich Holtmann,
Thomas Benner:
Adaptation of partitioning and high-level synthesis in hardware/software co-synthesis.
ICCAD 1994: 96-100 |
| 1993 |
|---|
| 2 | | W. Ye,
Rolf Ernst,
Thomas Benner,
Jörg Henkel:
Fast Timing Analysis for Hardware-Software Co-Synthesis.
ICCD 1993: 452-457 |
| 1 | EE | Rolf Ernst,
Jörg Henkel,
Thomas Benner:
Hardware-Software Cosynthesis for Microcontrollers.
IEEE Design & Test of Computers 10(4): 64-75 (1993) |
