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Masanori Hashimoto Vis

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*2009
62EEHiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction. ASP-DAC 2009: 266-271
61EELing Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng: High performance on-chip differential signaling using passive compensation for global communication. ASP-DAC 2009: 385-390
60EEShingo Watanabe, Masanori Hashimoto, Toshinori Sato: A case for exploiting complex arithmetic circuits towards performance yield enhancement. ISQED 2009: 401-407
59EETakashi Enami, Shinyu Ninomiya, Masanori Hashimoto: Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise. IEEE Trans. on CAD of Integrated Circuits and Systems 28(4): 541-553 (2009)
58EETakaaki Okumura, Atsushi Kurokawa, Hiroo Masuda, Toshiki Kanamoto, Masanori Hashimoto, Hiroshi Takafuji, Hidenari Nakashima, Nobuto Ono, Tsuyoshi Sakata, Takashi Sato: Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations. IEICE Transactions 92-A(4): 990-997 (2009)
57EEKoichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability. IEICE Transactions 92-C(2): 281-285 (2009)
2008
56EEKoichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --. ACM Great Lakes Symposium on VLSI 2008: 387-390
55EEYasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye: Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification. ASP-DAC 2008: 107-108
54EELing Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, Masanori Hashimoto: High performance current-mode differential logic. ASP-DAC 2008: 720-725
53EETakashi Enami, Masanori Hashimoto, Takashi Sato: Decoupling capacitance allocation for timing with statistical noise model and timing analysis. ICCAD 2008: 420-425
52EEYulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng: On-chip high performance signaling using passive compensation. ICCD 2008: 182-187
51EEHiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits. ISLPED 2008: 3-8
50EETakashi Enami, Shinyu Ninomiya, Masanori Hashimoto: Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise. ISPD 2008: 160-167
49EEShinya Abe, Masanori Hashimoto, Takao Onoye: Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution. ISQED 2008: 520-525
48EEToshiki Kanamoto, Yasuhiro Ogasahara, Keiko Natsume, Kenji Yamaguchi, Hiroyuki Amishiro, Tetsuya Watanabe, Masanori Hashimoto: Impact of Well Edge Proximity Effect on Timing. IEICE Transactions 91-A(12): 3461-3464 (2008)
47EEMasanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng: Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration. IEICE Transactions 91-A(12): 3474-3480 (2008)
46EEShinya Abe, Masanori Hashimoto, Takao Onoye: Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution. IEICE Transactions 91-A(12): 3481-3487 (2008)
45EEYukio Mitsuyama, Kazuma Takahashi, Rintaro Imai, Masanori Hashimoto, Takao Onoye, Isao Shirakawa: Area-Efficient Reconfigurable Architecture for Media Processing. IEICE Transactions 91-A(12): 3651-3662 (2008)
44EEMasanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera: Timing Analysis Considering Temporal Supply Voltage Fluctuation. IEICE Transactions 91-D(3): 655-660 (2008)
2007
43EEKenichi Shinkai, Masanori Hashimoto, Takao Onoye: Future Prediction of Self-Heating in Short Intra-Block Wires. ISQED 2007: 660-665
42EEMasanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera: Timing Analysis Considering Spatial Power/Ground Level Variation. IEICE Transactions 90-A(12): 2661-2668 (2007)
41EEMasanori Hashimoto, Takahito Ijichi, Shingo Takahashi, Shuji Tsukiyama, Isao Shirakawa: Transistor Sizing of LCD Driver Circuit for Technology Migration. IEICE Transactions 90-A(12): 2712-2717 (2007)
40EEYasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye: Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect. IEICE Transactions 90-A(4): 724-731 (2007)
39EEHiroyuki Kobayashi, Nobuto Ono, Takashi Sato, Jiro Iwai, Hidenari Nakashima, Takaaki Okumura, Masanori Hashimoto: Proposal of Metrics for SSTA Accuracy Evaluation. IEICE Transactions 90-A(4): 808-814 (2007)
38EEAkira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling. IEICE Transactions 90-C(6): 1267-1273 (2007)
2006
37EEAkira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Interconnect RL extraction at a single representative frequency. ASP-DAC 2006: 515-520
36EEKenichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye: A gate delay model focusing on current fluctuation over wide-range of process and environmental variability. ICCAD 2006: 47-53
35EEYasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye: Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects. ICCD 2006
34EETakashi Sato, Junji Ichimiya, Nobuto Ono, Masanori Hashimoto: On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature. IEICE Transactions 89-A(12): 3491-3499 (2006)
33EEShingo Takahashi, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa: A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays. IEICE Transactions 89-A(12): 3538-3545 (2006)
32EEToshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto: Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design. IEICE Transactions 89-A(12): 3560-3568 (2006)
31EEAkira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line. IEICE Transactions 89-A(12): 3585-3593 (2006)
30EEToshiki Kanamoto, Shigekiyo Akutsu, Tamiyo Nakabayashi, Takahiro Ichinomiya, Koutaro Hachiya, Atsushi Kurokawa, Hiroshi Ishikawa, Sakae Muromoto, Hiroyuki Kobayashi, Masanori Hashimoto: Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation. IEICE Transactions 89-A(12): 3666-3670 (2006)
2005
29EEYoshihiro Uchida, Sadahiro Tani, Masanori Hashimoto, Shuji Tsukiyama, Isao Shirakawa: Interconnect capacitance extraction for system LCD circuits. ACM Great Lakes Symposium on VLSI 2005: 160-163
28EETakashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto: On-chip thermal gradient analysis and temperature flattening for SoC design. ASP-DAC 2005: 1074-1077
27EEAkira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Return path selection for loop RL extraction. ASP-DAC 2005: 1078-1081
26EEMasanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera: Timing analysis considering temporal supply voltage fluctuation. ASP-DAC 2005: 1098-1101
25EETakashi Sato, Masanori Hashimoto, Hidetoshi Onodera: Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion. ASP-DAC 2005: 723-728
24EEAkinori Shinmyo, Masanori Hashimoto, Hidetoshi Onodera: Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18µm CMOS process. ASP-DAC 2005: 9-10
23EEAtsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera: Effects of on-chip inductance on power distribution grid. ISPD 2005: 63-69
22EEMasanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera: Statistical Analysis of Clock Skew Variation in H-Tree Structure. ISQED 2005: 402-407
21EEMasanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera: Statistical Analysis of Clock Skew Variation in H-Tree Structure. IEICE Transactions 88-A(12): 3375-3381 (2005)
20EETakashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto: On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design. IEICE Transactions 88-A(12): 3382-3389 (2005)
19EETakashi Sato, Masanori Hashimoto, Hidetoshi Onodera: Successive Pad Assignment for Minimizing Supply Voltage Drop. IEICE Transactions 88-A(12): 3429-3436 (2005)
18EEAtsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda: Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance. IEICE Transactions 88-A(12): 3453-3462 (2005)
17EEAtsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera: Effects of On-Chip Inductance on Power Distribution Grid. IEICE Transactions 88-A(12): 3564-3572 (2005)
16EEAkira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling. IEICE Transactions 88-A(4): 885-891 (2005)
15EETakahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera: A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL. IEICE Transactions 88-C(3): 437-444 (2005)
2004
14EETakahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera: A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process. ASP-DAC 2004: 545-546
13EEAkira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Representative frequency for interconnect R(f)L(f)C extraction. ASP-DAC 2004: 691-696
12EEMasanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera: Timing analysis considering spatial power/ground level variation. ICCAD 2004: 814-820
11EEMasanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera: Automatic Generation of Standard Cell Library in VDSM Technologies. ISQED 2004: 36-41
10EEMasanori Hashimoto, Yuji Yamada, Hidetoshi Onodera: Equivalent waveform propagation for static timing analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 498-508 (2004)
2003
9EEMasanori Hashimoto, Yuji Yamada, Hidetoshi Onodera: Equivalent Waveform Propagation for Static Timing Analysis. ICCAD 2003: 169-175
8EEMasanori Hashimoto, Yuji Yamada, Hidetoshi Onodera: Capturing crosstalk-induced waveform for accurate static timing analysis. ISPD 2003: 18-23
2002
7EEMasanori Hashimoto, Masao Takahashi, Hidetoshi Onodera: Crosstalk noise optimization by post-layout transistor sizing. ISPD 2002: 126-130
6 Masanori Hashimoto, Yashiteru Hayashi, Hidetoshi Onodera: Experimental Study on Cell-Base High-Performance Datapath Design. IWLS 2002: 283-287
2001
5EEMasanori Hashimoto, Hidetoshi Onodera: Post-layout transistor sizing for power reduction in cell-based design. ASP-DAC 2001: 359-365
4 Masao Takahashi, Masanori Hashimoto, Hidetoshi Onodera: Crosstalk Noise Estimation for Generic RC Trees. ICCD 2001: 110-117
2000
3EEMasanori Hashimoto, Hidetoshi Onodera: A performance optimization method by gate sizing using statistical static timing analysis. ISPD 2000: 111-116
1999
2EEMasanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru: A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. DAC 1999: 446-451
1998
1EEMasanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru: A power optimization method considering glitch reduction by gate sizing. ISLPED 1998: 221-226

Coauthor Index

1Shinya Abe [46] [49]
2Shigekiyo Akutsu [30]
3Hiroyuki Amishiro [48]
4Chung-Kuan Cheng [47] [52] [54] [61]
5Takashi Enami [50] [53] [59]
6Kazunori Fujimori [11]
7Hiroshi Fuketa [51] [56] [57] [62]
8Koutaro Hachiya [20] [28] [30]
9Koichi Hamamoto [56] [57]
10Yashiteru Hayashi [6]
11Zhangcai Huang [18]
12Junji Ichimiya [20] [28] [34]
13Takahiro Ichinomiya [30]
14Takahito Ijichi [41]
15Tatsuhiko Ikeda [32]
16Rintaro Imai [45]
17Ryosuke Inagaki [18]
18Yasuaki Inoue [18]
19Hiroshi Ishikawa [30]
20Jiro Iwai [39]
21Toshiki Kanamoto [30] [32] [48] [58]
22Akira Kasebe [18]
23Hiroyuki Kobayashi [30] [39]
24Ernest S. Kuh [61]
25Atsushi Kurokawa [18] [30] [36] [58]
26Jianhua Liu [54]
27Hiroo Masuda [18] [58]
28Yukio Mitsuyama [45] [51] [56] [57] [62]
29Takahito Miyazaki [14] [15]
30Atsushi Muramatsu [17] [23]
31Sakae Muromoto [30]
32Tamiyo Nakabayashi [30]
33Hidenari Nakashima [39] [58]
34Keiko Natsume [48]
35Shinyu Ninomiya [50] [59]
36Yasuhiro Ogasahara [35] [40] [48] [55]
37Takaaki Okumura [39] [58]
38Nobuto Ono [20] [28] [34] [39] [58]
39Hidetoshi Onodera [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [19] [21] [22] [23] [24] [25] [26] [27] [31] [32] [37] [38] [42] [44]
40Takao Onoye [35] [36] [40] [43] [45] [46] [49] [51] [55] [56] [57] [62]
41Tsuyoshi Sakata [58]
42Takashi Sato [19] [20] [25] [26] [28] [34] [39] [44] [53] [58]
43Toshinori Sato [60]
44Kenichi Shinkai [36] [43]
45Akinori Shinmyo [24]
46Isao Shirakawa [29] [33] [41] [45]
47Jangsombatsiri Siriporn [47]
48Hiroshi Takafuji [58]
49Kazuma Takahashi [45]
50Masao Takahashi [4] [7]
51Shingo Takahashi [33] [41]
52Keikichi Tamaru [1] [2]
53Sadahiro Tani [29]
54Akira Tsuchiya [13] [16] [27] [31] [32] [37] [38] [47] [52] [61]
55Shuji Tsukiyama [29] [33] [41]
56Yoshihiro Uchida [29]
57Shingo Watanabe [60]
58Tetsuya Watanabe [48]
59Yuji Yamada [8] [9] [10]
60Junji Yamaguchi [12] [26] [42] [44]
61Kenji Yamaguchi [48]
62Tomonori Yamamoto [21] [22]
63Yun Yang [18]
64Ling Zhang [52] [54] [61]
65Yulei Zhang [52] [61]
66Haikun Zhu [47] [54]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)