| |
| 1998 | ||
|---|---|---|
| 3 | Fran Hanchek, Shantanu Dutt: Methodologies for Tolerating Cell and Interconnect Faults in FPGAs. IEEE Trans. Computers 47(1): 15-33 (1998) | |
| 1997 | ||
| 2 | EE | Shantanu Dutt, Fran Hanchek: REMOD: a new methodology for designing fault-tolerant arithmetic circuits. IEEE Trans. VLSI Syst. 5(1): 34-56 (1997) |
| 1996 | ||
| 1 | EE | Fran Hanchek, Shantanu Dutt: Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs. VLSI Design 1996: 225-229 |
| 1 | Shantanu Dutt | [1] [2] [3] |