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Toshihiro Hanawa Vis

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*2009
11EEShin'ichi Miura, Toshihiro Hanawa, Taiga Yonemoto, Taisuke Boku, Mitsuhisa Sato: RI2N/DRV: Multi-link ethernet for high-bandwidth and fault-tolerant network on PC clusters. IPDPS 2009: 1-7
10EEToshihiro Hanawa, Mitsuhisa Sato, Jinpil Lee, Takayuki Imada, Hideaki Kimura, Taisuke Boku: Evaluation of Multicore Processors for Embedded Systems by Parallel Benchmark Program Using OpenMP. IWOMP 2009: 15-27
2008
9EEShin'ichi Miura, Takayuki Okamoto, Taisuke Boku, Toshihiro Hanawa, Mitsuhisa Sato: RI2N: High-bandwidth and fault-tolerant network with multi-link Ethernet for PC clusters. CLUSTER 2008: 274-279
8EEShin'ichi Miura, Taisuke Boku, Takayuki Okamoto, Toshihiro Hanawa: A dynamic routing control system for high-performance PC cluster with multi-path Ethernet connection. IPDPS 2008: 1-8
2005
7 Toshihiro Hanawa, Toshiya Minai, Yasuki Tanabe, Hideharu Amano: Implementation of ISIS-SimpleScalar. PDPTA 2005: 117-123
6EETakashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Yasuki Tanabe, Toshihiro Hanawa, Hideharu Amano: The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism). Parallel Computing 31(3-4): 352-370 (2005)
2003
5 Yasuki Tanabe, Takashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Toshihiro Hanawa, Hideharu Amano: Performance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mechanism. PDPTA 2003: 1148-1154
1999
4 Junji Yamamoto, Takashi Fujiwara, T. Komeda, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano: Performance evaluation of SNAIL: A multiprocessor based on the simple serial synchronized multistage interconnection network architecture. Parallel Computing 25(9): 1081-1103 (1999)
1998
3 Takashi Midorikawa, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano: The MINC (Multistage Interconnection Network with Cache Control Mechanism) Chip. ASP-DAC 1998: 337-338
1997
2 Akira Funahashi, Toshihiro Hanawa, Hideharu Amano, Tomohiro Kudoh: Adaptive Routing on the Recursive Diagonal Torus. ISHPC 1997: 171-182
1994
1 Toshihiro Hanawa, Hideharu Amano, Yoshifumi Fujikawa: Multistage Interconnection Networks with Multiple Outlets. ICPP (1) 1994: 1-8

Coauthor Index

1Hideharu Amano [1] [2] [3] [4] [5] [6] [7]
2Taisuke Boku [8] [9] [10] [11]
3Yoshifumi Fujikawa [1]
4Takashi Fujiwara [4]
5Akira Funahashi [2]
6Takayuki Imada [10]
7Takayuki Kamei [3] [4]
8Hideaki Kimura [10]
9T. Komeda [4]
10Tomohiro Kudoh [2]
11Jinpil Lee [10]
12Takashi Midorikawa [3] [5] [6]
13Toshiya Minai [7]
14Shin'ichi Miura [8] [9] [11]
15Takayuki Okamoto [8] [9]
16Mitsuhisa Sato [9] [10] [11]
17Masayoshi Shigeno [5] [6]
18Daisuke Shiraishi [5] [6]
19Yasuki Tanabe [5] [6] [7]
20Junji Yamamoto [4]
21Taiga Yonemoto [11]

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)