| 2007 |
|---|
| 36 | EE | Jong-Suk Lee,
Dong Sam Ha:
High Speed 1-bit Bypass Adder Design for Low Precision Additions.
ISCAS 2007: 1093-1096 |
| 35 | EE | Rajesh Thirugnanam,
Dong Sam Ha,
T. M. Mak:
Data Recovery Block Design for Impulse Modulated Power Line Communications in a Microprocessor.
ISVLSI 2007: 153-158 |
| 2006 |
|---|
| 34 | EE | Rajesh Thirugnanam,
Dong Sam Ha,
Bong Hyuk Park,
S. S. Choi:
Design of a tunable fully differential GHz range Gm-C lowpass filter in 0.18µm CMOS for DS-CDMA UWB transceivers.
ISCAS 2006 |
| 33 | EE | Jong-Suk Lee,
Dong Sam Ha:
FleXilicon: a reconfigurable architecture for multimedia and wireless communications.
ISCAS 2006 |
| 2005 |
|---|
| 32 | EE | Jung-Ho Kim,
Dong Sam Ha,
Jeffrey H. Reed:
A new reconfigurable modem architecture for 3G multi-standard wireless communication systems.
ISCAS (2) 2005: 1051-1054 |
| 31 | EE | Woo Cheol Chung,
Dong Sam Ha,
Hyung-Jin Lee:
Dual use of power lines for data communications in a system-on-chip environment.
ISCAS (4) 2005: 3355-3358 |
| 30 | EE | Hyung-Jin Lee,
Dong Sam Ha,
S. S. Choi:
A systematic approach to CMOS low noise amplifier design for ultrawideband applications.
ISCAS (4) 2005: 3962-3965 |
| 2004 |
|---|
| 29 | | Venkat Srinivasan,
Dong Sam Ha,
Jos Sulistyo:
Gigahertz-range MCML multiplier architectures.
ISCAS (2) 2004: 785-788 |
| 28 | EE | N. J. August,
Dong Sam Ha:
Low power design of DCT and IDCT for low bit rate video codecs.
IEEE Transactions on Multimedia 6(3): 414-422 (2004) |
| 2003 |
|---|
| 27 | EE | Suk Won Kim,
Dong Sam Ha,
Jeffrey H. Reed:
Minimum selection GSC and adaptive low-power rake combining scheme.
ISCAS (4) 2003: 357-360 |
| 26 | EE | Jos Sulistyo,
Dong Sam Ha:
5 GHz pipelined multiplier and MAC in 0.18µm complementary static CMOS.
ISCAS (5) 2003: 117-120 |
| 25 | EE | Hyung-Jin Lee,
Dong Sam Ha:
Frequency Domain Approach for CMOS Ultra-Wideband Radios.
ISVLSI 2003: 236-237 |
| 2002 |
|---|
| 24 | EE | Takahiro J. Yamaguchi,
Dong Sam Ha,
Masahiro Ishida,
Tadahiro Ohmi:
A Method for Compressing Test Data Based on Burrows-Wheeler Transformation.
IEEE Trans. Computers 51(5): 486-497 (2002) |
| 2001 |
|---|
| 23 | EE | M. Jagasivamani,
Dong Sam Ha:
Development of a low-power SRAM compiler.
ISCAS (4) 2001: 498-501 |
| 2000 |
|---|
| 22 | EE | Sungjoo Yoo,
Kiyoung Choi,
Dong Sam Ha:
Performance improvement of geographically distributed cosimulation by hierarchically grouped messages.
IEEE Trans. VLSI Syst. 8(5): 492-502 (2000) |
| 21 | EE | Han Bin Kim,
Dong Sam Ha,
Takeshi Takahashi,
Takahiro J. Yamaguchi:
A new approach to built-in self-testable datapath synthesis based on integer linear programming.
IEEE Trans. VLSI Syst. 8(5): 594-605 (2000) |
| 1999 |
|---|
| 20 | EE | Han Bin Kim,
Dong Sam Ha,
Takeshi Takahashi:
On ILP Formulations for Built-In Self-Testable Data Path Synthesis.
DAC 1999: 742-747 |
| 19 | | Han Bin Kim,
Dong Sam Ha:
A high-level BIST synthesis method based on a region-wise heuristic for an integer linear programming.
ITC 1999: 903-912 |
| 1998 |
|---|
| 18 | EE | Han Bin Kim,
Takeshi Takahashi,
Dong Sam Ha:
Test session oriented built-in self-testable data path synthesis.
ITC 1998: 154-163 |
| 17 | EE | Masahiro Ishida,
Dong Sam Ha,
Takahiro J. Yamaguchi:
COMPACT: A Hybrid Method for Compressing Test Data.
VTS 1998: 62-69 |
| 1997 |
|---|
| 16 | | Takahiro J. Yamaguchi,
Masahiro Ishida,
Marco Tilgner,
Dong Sam Ha:
An Efficient Method for Compressing Test Data.
ITC 1997: 79-88 |
| 1996 |
|---|
| 15 | EE | Hyung Ki Lee,
Dong Sam Ha:
HOPE: an efficient parallel fault simulator for synchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1048-1058 (1996) |
| 1995 |
|---|
| 14 | | Insung Park,
Dong Sam Ha,
Gyoochan Sim:
A New Method for Partial Scan Design Based on Propagation and Justification Requirements of Faults.
ITC 1995: 413-422 |
| 13 | EE | Rajesh Nair,
Dong Sam Ha:
VISION: an efficient parallel pattern fault simulator for synchronous sequential circuits.
VTS 1995: 221-226 |
| 1993 |
|---|
| 12 | EE | Hyung Ki Lee,
Dong Sam Ha:
New methods of improving parallel fault simulation in synchronous sequential circuits.
ICCAD 1993: 10-17 |
| 1992 |
|---|
| 11 | EE | Hyung Ki Lee,
Dong Sam Ha:
HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits.
DAC 1992: 336-340 |
| 1991 |
|---|
| 10 | | Hyung Ki Lee,
Dong Sam Ha:
An Efficient, Forward Fault Simulation Algorithm Based on the Parallel Pattern Single Fault Propagation.
ITC 1991: 946-955 |
| 1990 |
|---|
| 9 | EE | Hyung Ki Lee,
Dong Sam Ha:
SOPRANO: An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits.
DAC 1990: 660-666 |
| 8 | | Dong Sam Ha,
Vijay P. Kumar:
On the Design of High-Yield Reconfigurable PLA's.
IEEE Trans. Computers 39(4): 470-479 (1990) |
| 1989 |
|---|
| 7 | EE | Hyung Ki Lee,
Dong Sam Ha,
K. Kim:
Test Generation of Stuck-open Faults Using Stuck-at Test Sets in CMOS Combinational Circuits.
DAC 1989: 345-350 |
| 1988 |
|---|
| 6 | EE | Kwanghyun Kim,
Joseph G. Tront,
Dong Sam Ha:
Automatic Insertion of BIST Hardware Using VHDL.
DAC 1988: 9-15 |
| 5 | | Dong Sam Ha,
Sudhakar M. Reddy:
On the Design of Pseudoexhaustive Testable PLA's.
IEEE Trans. Computers 37(4): 468-472 (1988) |
| 4 | EE | Kwanghyun Kim,
Dong Sam Ha,
Joseph G. Tront:
On using signature registers as pseudorandom pattern generators in built-in self-testing.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(8): 919-928 (1988) |
| 1987 |
|---|
| 3 | | Sudhakar M. Reddy,
Dong Sam Ha:
A New Approach to the Design of Testable PLA's.
IEEE Trans. Computers 36(2): 201-211 (1987) |
| 1986 |
|---|
| 2 | | Dong Sam Ha,
Sudhakar M. Reddy:
On the Design of Random Pattern Testable PLAs.
ITC 1986: 688-695 |
| 1985 |
|---|
| 1 | | Dong Sam Ha,
Sudhakar M. Reddy:
On the Design of Testable Domino PLAs.
ITC 1985: 567-573 |
