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Sandeep K. Gupta Vis

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*2008
107EEJae Chul Cha, Sandeep K. Gupta: Matrix Inversion on a PIM (Processor-in-Memory). CSSE (3) 2008: 419-422
106EEJae Chul Cha, Sandeep K. Gupta: Characterization of granularity and redundancy for SRAMs for optimal yield-per-area. ICCD 2008: 219-226
105EEJae Chul Cha, Sandeep K. Gupta: Data Partitioning and Placement Schemes for Matrix Multiplications on a PIM Architecture. ISPDC 2008: 309-316
104EEI-De Huang, Yi-Shing Chang, Sandeep K. Gupta, Sreejit Chakravarty: An Industrial Case Study of Sticky Path-Delay Faults. VTS 2008: 395-402
103EEJung-Yup Kang, Sandeep K. Gupta, Jean-Luc Gaudiot: An Efficient Data-Distribution Mechanism in a Processor-In-Memory (PIM) Architecture Applied to Motion Estimation. IEEE Trans. Computers 57(3): 375-388 (2008)
2007
102EEHugo Cheung, Sandeep K. Gupta: Accurate modeling and fault simulation of Byzantine resistive bridges. ICCD 2007: 347-353
2006
101EEShahin Nazarian, Massoud Pedram, Sandeep K. Gupta, Melvin A. Breuer: STAX: statistical crosstalk target set compaction. DATE Designers' Forum 2006: 172-177
100EEKun Young Chung, Sandeep K. Gupta: Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time Borrowing. VTS 2006: 8-15
99EESeongmoon Wang, Sandeep K. Gupta: LT-RTPG: a new test-per-scan BIST TPG for low switching activity. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1565-1574 (2006)
2005
98EEWichian Sirisaengtaksin, Sandeep K. Gupta: A Methodology to Compute Bounds on Crosstalk Effects in Arbitrary Interconnects. Asian Test Symposium 2005: 112-119
97EEI-De Huang, Sandeep K. Gupta: Selection of Paths for Delay Testing. Asian Test Symposium 2005: 208-215
96EEZhigang Jiang, Sandeep K. Gupta: Threshold testing: Covering bridging and other realistic faults. Asian Test Symposium 2005: 390-397
2004
95EEMelvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian: Efficient Identification of Crosstalk Induced Slowdown Targets. Asian Test Symposium 2004: 124-131
94EEWichian Sirisaengtaksin, Sandeep K. Gupta: Modeling and Testing Crosstalk Faults in Inter-Core Interconnects that Include Tri-State and Bi-Directional Nets. Asian Test Symposium 2004: 132-139
93EELei Wang, Sandeep K. Gupta, Melvin A. Breuer: Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects. Asian Test Symposium 2004: 440-447
92EEShahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer: Timing-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault Models. ITC 2004: 1024-1033
91EEMd. Saffat Quasem, Sandeep K. Gupta: Designing Reconfigurable Multiple Scan Chains for Systems-on-Chip. VTS 2004: 367-376
90EEMelvin A. Breuer, Sandeep K. Gupta, T. M. Mak: Defect and Error Tolerance in the Presence of Massive Numbers of Defects. IEEE Design & Test of Computers 21(3): 216-227 (2004)
2003
89EEArani Sinha, Sandeep K. Gupta, Melvin A. Breuer: An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults. Asian Test Symposium 2003: 174-177
88EEZhigang Jiang, Sandeep K. Gupta: A Test Generation Approach for Systems-on-Chip that Use Intellectual Property Cores. Asian Test Symposium 2003: 278-283
87EEMd. Saffat Quasem, Sandeep K. Gupta: Designing Multiple Scan Chains for Systems-on-Chip. Asian Test Symposium 2003: 424-427
86EEKun Young Chung, Sandeep K. Gupta: Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing. ITC 2003: 1089-1097
85EEYi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer: Test Generation for Maximizing Ground Bounce Considering Circuit Delay. VTS 2003: 151-157
84EENabil M. Abdulrazzaq, Sandeep K. Gupta: Path-Delay Fault Simulation for Circuits with Large Numbers of Paths for Very Large Test Sets. VTS 2003: 186-196
83EESultan M. Al-Harbi, Sandeep K. Gupta: Generating Complete and Optimal March Tests for Linked Faults in Memories. VTS 2003: 254-266
82EEShahdad Irajpour, Shahin Nazarian, Lei Wang, Sandeep K. Gupta, Melvin A. Breuer: Analyzing Crosstalk in the Presence of Weak Bridge Defects. VTS 2003: 385-392
81EEMd. Saffat Quasem, Zhigang Jiang, Sandeep K. Gupta: Benefits of a SoC-Specific Test Methodology. IEEE Design & Test of Computers 20(3): 68-77 (2003)
2002
80EEWichian Sirisaengtaksin, Sandeep K. Gupta: Enhanced Crosstalk Fault Model and Methodology to Generate Tests for Arbitrary Inter-core Interconnect Topology. Asian Test Symposium 2002: 163-169
79EEI-De Huang, Sandeep K. Gupta, Melvin A. Breuer: Accurate and Efficient Static Timing Analysis with Crosstalk. ICCD 2002: 265-272
78EEShahin Nazarian, Hang Huang, Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer: XIDEN: Crosstalk Target Identification Framework. ITC 2002: 365-374
77EEZhigang Jiang, Sandeep K. Gupta: An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes. ITC 2002: 824-833
76EEWei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer: Analytical models for crosstalk excitation and propagation in VLSI circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1117-1131 (2002)
75EESeongmoon Wang, Sandeep K. Gupta: DS-LFSR: a BIST TPG for low switching activity. IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 842-851 (2002)
74EESeongmoon Wang, Sandeep K. Gupta: An automatic test pattern generator for minimizing switching activity during scan testing activity. IEEE Trans. on CAD of Integrated Circuits and Systems 21(8): 954-968 (2002)
73EEWei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer: Test Generation for Crosstalk-Induced Faults: Framework and Computational Results. J. Electronic Testing 18(1): 17-28 (2002)
72EELiang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer: TA-PSV - Timing Analysis for Partially Specified Vectors. J. Electronic Testing 18(1): 73-88 (2002)
2001
71EELiang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer: A New Gate Delay Model for Simultaneous Switching and Its Applications. DAC 2001: 289-294
70EEMd. Saffat Quasem, Sandeep K. Gupta: Exact fault simulation for systems on Silicon that protects each core's intellectual property. DATE 2001: 804
69 Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer: Switch-level delay test of domino logic circuits. ITC 2001: 367-376
68 Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer: Crosstalk test generation on pseudo industrial circuits: a case study. ITC 2001: 548-557
67EESultan M. Al-Harbi, Sandeep K. Gupta: An Efficient Methodology for Generating Optimal and Uniform March Tests. VTS 2001: 231-239
66EEYi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer: Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out. VTS 2001: 358-367
65EEIshwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Introducing redundant computations in RTL data paths for reducing BIST resources. ACM Trans. Design Autom. Electr. Syst. 6(3): 423-445 (2001)
64EEPankaj Pant, Yuan-Chieh Hsu, Sandeep K. Gupta, Abhijit Chatterjee: Path delay fault diagnosis in combinational circuits with implicitfault enumeration. IEEE Trans. on CAD of Integrated Circuits and Systems 20(10): 1226-1235 (2001)
2000
63EELiang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer: A new framework for static timing analysis, incremental timing refinement, and timing simulation. Asian Test Symposium 2000: 102-107
62EEWei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer: Test generation for crosstalk-induced faults: framework and computational result. Asian Test Symposium 2000: 305-310
61EEChen-Huan Chiang, Sandeep K. Gupta: BIST TPG for SRAM cluster interconnect testing at board level. Asian Test Symposium 2000: 58-65
60EESandeep K. Gupta, Wang-Chien Lee, Pradip K. Srimani: Message from the Chairs. ICPP Workshops 2000: 3
59 Nabil M. Abdulrazzaq, Sandeep K. Gupta: Test generation for path-delay faults in one-dimensional iterative logic arrays. ITC 2000: 326-335
58 Melvin A. Breuer, Sandeep K. Gupta: New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits. VLSI Design 2000: 8
57EEHugo Cheung, Sandeep K. Gupta: A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study. VTS 2000: 89-96
56EERajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer: Novel Test Pattern Generators for Pseudoexhaustive Testing. IEEE Trans. Computers 49(11): 1228-1240 (2000)
55EEChen-Huan Chiang, Sandeep K. Gupta: BIST TPG for Combinational Cluster Interconnect Testing at Board Level. J. Electronic Testing 16(5): 427-442 (2000)
1999
54EEArani Sinha, Sandeep K. Gupta, Melvin A. Breuer: Validation and test generation for oscillatory noise in VLSI interconnects. ICCAD 1999: 289-296
53 Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer: Switch-level delay test. ITC 1999: 171-180
52 Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer: Test generation for crosstalk-induced delay in integrated circuits. ITC 1999: 191-200
51 Seongmoon Wang, Sandeep K. Gupta: LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation. ITC 1999: 85-94
50EEYi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer: Test Generation for Ground Bounce in Internal Logic Circuitry. VTS 1999: 95-105
1998
49EEChen-Huan Chiang, Sandeep K. Gupta: BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level. Asian Test Symposium 1998: 244-252
48EEYuan-Chieh Hsu, Sandeep K. Gupta: An Automatic Test Pattern Generator for At-Speed Robust Path Delay Testing. Asian Test Symposium 1998: 88-95
47EEIshwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Introducing Redundant Computations in a Behavior for Reducing BIST Resources. DAC 1998: 548-553
46EEIshwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Scheduling and Module Assignment for Reducing Bist Resources. DATE 1998: 66-73
45EESuriyaprakash Natarajan, Melvin A. Breuer, Sandeep K. Gupta: Process Variations and their Impact on Circuit Operation. DFT 1998: 73-
44EEWeiyu Chen, Sandeep K. Gupta, Melvin A. Breuer: Test generation in VLSI circuits for crosstalk noise. ITC 1998: 641-
43EEYuan-Chieh Hsu, Sandeep K. Gupta: A new path-oriented effect-cause methodology to diagnose delay failures. ITC 1998: 758-
42EESultan M. Al-Harbi, Sandeep K. Gupta: A Methodology for Transforming Memory Tests for In-System Testing of Direct Mapped Cache Tags. VTS 1998: 394-400
41 Seongmoon Wang, Sandeep K. Gupta: ATPG for Heat Dissipation Minimization During Test Application. IEEE Trans. Computers 47(2): 256-262 (1998)
40EERajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer: Bounds on pseudoexhaustive test lengths. IEEE Trans. VLSI Syst. 6(3): 420-431 (1998)
39EEChih-Ang Chen, Sandeep K. Gupta: Efficient BIST TPG design and test set compaction via input reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 692-705 (1998)
38EEIshwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Allocation Techniques for Reducing BIST Area Overhead of Data Paths. J. Electronic Testing 13(2): 149-166 (1998)
37EEIshwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Estimation of BIST Resources During High-Level Synthesis. J. Electronic Testing 13(3): 221-237 (1998)
1997
36EESeongmoon Wang, Sandeep K. Gupta: ATPG for Heat Dissipation Minimization During Scan Testing. DAC 1997: 614-619
35EEChen-Huan Chiang, Sandeep K. Gupta: BIST TPG for faults in system backplanes. ICCAD 1997: 406-413
34 Weiyu Chen, Melvin A. Breuer, Sandeep K. Gupta: Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs. ITC 1997: 809-818
33 Seongmoon Wang, Sandeep K. Gupta: DS-LFSR: A New BIST TPG for Low Heat Dissipation. ITC 1997: 848-857
32EEYi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer: Analysis of Ground Bounce in Deep Sub-Micron Circuits. VTS 1997: 110-116
31EEChen-Huan Chiang, Sandeep K. Gupta: BIST TPGs for Faults in Board Level Interconnect via Boundary Scan. VTS 1997: 376-383
30EELiang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer: High Quality Robust Tests for Path Delay Faults. VTS 1997: 88-93
1996
29EEIshwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Lower Bounds on Test Resources for Scheduled Data Flow Graphs. DAC 1996: 143-148
28EEChih-Ang Chen, Sandeep K. Gupta: A Satisfiability-Based Test Generator for Path Delay Faults in Combinational Circuts. DAC 1996: 209-214
27 Zhiyong Li, John H. Reif, Sandeep K. Gupta: Synthesizing Efficient Out-of-Core Programs for Block Recursive Algorithms Using Block-Cyclic Data Distributions. ICPP, Vol. 2 1996: 142-149
26 Hugo Cheung, Sandeep K. Gupta: A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation. ITC 1996: 386-395
25 Melvin A. Breuer, Sandeep K. Gupta: Process-Aggravated Noise (PAN): New Validation and Test Problems. ITC 1996: 914-923
24EESandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma: Delay Fault Testing: How Robust are Our Models? VTS 1996: 502-503
23 Sandeep K. Gupta, Dhiraj K. Pradhan: Utilization of On-Line (Concurrent) Checkers During Built-In-Self-Test and Vice Versa. IEEE Trans. Computers 45(1): 63-73 (1996)
22 Yuan-Chieh Hsu, Sandeep K. Gupta: A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits. IEEE Trans. Computers 45(11): 1312-1318 (1996)
21 Chih-Ang Chen, Sandeep K. Gupta: BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms. IEEE Trans. Computers 45(3): 257-269 (1996)
20EEChih-Ang Chen, Sandeep K. Gupta: Design of efficient BIST test pattern generators for delay testing. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1568-1575 (1996)
1995
19 Sandeep K. Gupta, John D. Kececioglu, Alejandro A. Schäffer: Making the Shortest-Paths Approach to Sum-of-Pairs Multiple Sequence Alignment More Space Efficient in Practice (Extended Abstract). CPM 1995: 128-143
18EEIshwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead. DAC 1995: 395-401
17 Chih-Ang Chen, Sandeep K. Gupta: A Methodology to Design Efficient BIST Test Pattern Generators. ITC 1995: 814-823
16 Mody Lempel, Sandeep K. Gupta: Zero Aliasing for Modeled Faults. IEEE Trans. Computers 44(11): 1283-1295 (1995)
15EEMody Lempel, Sandeep K. Gupta, Melvin A. Breuer: Test embedding with discrete logarithms. IEEE Trans. on CAD of Integrated Circuits and Systems 14(5): 554-566 (1995)
14 Sandeep K. Gupta, John D. Kececioglu, Alejandro A. Schäffer: Improving the Practical Space and Time Efficiency of the Shortest-Paths Approach to Sum-of-Pairs Multiple Sequence Alignment. Journal of Computational Biology 2(3): 459-472 (1995)
1994
13EEWen-Chang Fang, Sandeep K. Gupta: Clock Grouping: A Low Cost DFT Methodology for Delay Testing. DAC 1994: 94-99
12 Sen-Pin Lin, Sandeep K. Gupta, Melvin A. Breuer: A Low Cost BIST Methodology and Associated Novel Test Pattern Generator. EDAC-ETC-EUROASIC 1994: 106-112
11 Chih-Ang Chen, Sandeep K. Gupta: BIST Test Pattern Generators for Stuck-Open and Delay Testing. EDAC-ETC-EUROASIC 1994: 289-296
10EEChen-Huan Chiang, Sandeep K. Gupta: Random pattern testable logic synthesis. ICCAD 1994: 125-128
9 Seongmoon Wang, Sandeep K. Gupta: ATPG for Heat Dissipation Minimization During Test Application. ITC 1994: 250-258
1993
8EERajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer: An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing. DAC 1993: 242-248
7 Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer: Novel Test Pattern Generators for Pseudo-Exhaustive Testing. ITC 1993: 1041-1050
1992
6 Sandeep K. Gupta, Dhiraj K. Pradhan: Can Concurrent Checkers Help BIST? ITC 1992: 140-150
1991
5 Mark G. Karpovsky, Sandeep K. Gupta, Dhiraj K. Pradhan: Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model. ITC 1991: 828-839
4 Dhiraj K. Pradhan, Sandeep K. Gupta: A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression. IEEE Trans. Computers 40(6): 743-763 (1991)
1990
3 Dhiraj K. Pradhan, Sandeep K. Gupta, Mark G. Karpovsky: Aliasing Probability for Multiple Input Signature Analyzer. IEEE Trans. Computers 39(4): 586-591 (1990)
1988
2 Sandeep K. Gupta, Dhiraj K. Pradhan: A New Framework for Designing and Analyzing BIST Techniques: Computation of Exact Aliasing Probability. ITC 1988: 329-342
1 Sandeep K. Gupta, Melvin A. Breuer, Jung-Cheun Lien: Concurrent Control of Multiple BIT Structures. ITC 1988: 431-442

Coauthor Index

1Nabil M. Abdulrazzaq [59] [84]
2Sultan M. Al-Harbi [42] [67] [83]
3Melvin A. Breuer [1] [7] [8] [12] [15] [18] [25] [29] [30] [32] [34] [37] [38] [40] [44] [45] [46] [47] [50] [52] [53] [54] [56] [58] [62] [63] [65] [66] [68] [69] [71] [72] [73] [76] [78] [79] [82] [85] [89] [90] [92] [93] [95] [101]
4Jae Chul Cha [105] [106] [107]
5Sreejit Chakravarty [104]
6Yi-Shing Chang [32] [50] [66] [85] [104]
7Abhijit Chatterjee [64]
8Chih-Ang Chen [11] [17] [20] [21] [28] [39]
9Liang-Chi Chen [30] [63] [68] [71] [72]
10Wei-Yu Chen [52] [62] [73] [76]
11Weiyu Chen [34] [44]
12Hugo Cheung [26] [57] [102]
13Chen-Huan Chiang [10] [31] [35] [49] [55] [61]
14Kun Young Chung [86] [100]
15Wen-Chang Fang [13]
16Jean-Luc Gaudiot [103]
17Yuan-Chieh Hsu [22] [43] [48] [64]
18Hang Huang [78]
19I-De Huang [79] [97] [104]
20Shahdad Irajpour [82] [92]
21Zhigang Jiang [77] [81] [88] [96]
22Jung-Yup Kang [103]
23Mark G. Karpovsky [3] [5]
24John D. Kececioglu [14] [19]
25Wang-Chien Lee [60]
26Mody Lempel [15] [16]
27Zhiyong Li [27]
28Jung-Cheun Lien [1]
29Sen-Pin Lin [12]
30T. M. Mak [68] [90]
31Suriyaprakash Natarajan [45] [53] [69] [78]
32Shahin Nazarian [78] [82] [95] [101]
33Pankaj Pant [64]
34Ishwar Parulkar [18] [29] [37] [38] [46] [47] [65]
35Massoud Pedram [101]
36Slawomir Pilarski [24]
37Dhiraj K. Pradhan [2] [3] [4] [5] [6] [23]
38Md. Saffat Quasem [70] [81] [87] [91]
39Sudhakar M. Reddy [24]
40John H. Reif [27]
41Jacob Savir [24]
42Alejandro A. Schäffer [14] [19]
43Arani Sinha [54] [89]
44Wichian Sirisaengtaksin [80] [94] [98]
45Pradip K. Srimani [60]
46Rajagopalan Srinivasan [7] [8] [40] [56]
47Prab Varma [24]
48Lei Wang [82] [93]
49Seongmoon Wang [9] [33] [36] [41] [51] [74] [75] [99]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)