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Jiun-In Guo Vis

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*2009
49EEHsiu-Cheng Chang, Yao-Chang Yang, Jia-Wei Chen, Ching-Lung Su, Cheng-An Chien, Jiun-In Guo, Jinn-Shyan Wang: A dynamic quality-scalable H.264 video encoder chip. ASP-DAC 2009: 125-126
48EEChin-Hsien Wang, Ching-Hwa Cheng, Jiun-In Guo: CKVdd: a self-stabilization ramp-vdd technique for dynamic power reduction. ASP-DAC 2009: 93-94
47EEChih-Da Chien, Cheng-An Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng: A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications. ACM Trans. Design Autom. Electr. Syst. 14(1): (2009)
2007
46EEJui-Chin Chu, Wei-Chun Ku, Shu-Hsuan Chou, Tien-Fu Chen, Jiun-In Guo: An Embedded Coherent-Multithreading Multimedia Processor and Its Programming Model. DAC 2007: 652-657
45EEChih-Da Chien, Chih-Wei Wang, Chiun-Chau Lin, Tien-Wei Hsieh, Yuan-Hwa Chu, Jiun-In Guo: A Low Latency Memory Controller for Video Coding Systems. ICME 2007: 1211-1214
44EEGuo-An Jian, Jiun-In Guo: Low Complexity Multi-Standard Video Player for Portable Multimedia Applications. ICME 2007: 7
43EEGuo-An Jian, Chih-Da Chien, Jiun-In Guo: A Memory-Based Hardware Accelerator for Real-Time MPEG-4 Audio Coding and Reverberation. ISCAS 2007: 1569-1572
42EEKuan-Hung Chen, Yuan-Sun Chu, Yu-Min Chen, Jiun-In Guo: A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique. ISCAS 2007: 3139-3142
41EEChun-Hao Chang, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Jinn-Shyan Wang, Jiun-In Guo: A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons. SiPS 2007: 521-526
2006
40EEChing-Lung Su, Wei-Sen Yang, Ya-Li Chen, Yao-Chang Yang, Ching-Wen Chen, Jiun-In Guo, Shau-Yin Tseng: A Low Complexity High Quality Interger Motion Estimation Architecture Design for H.264/AVC. APCCAS 2006: 398-401
39EEChing-Lung Su, Wei-Sen Yang, Ya-Li Chen, Yao Li, Ching-Wen Chen, Jiun-In Guo, Shau-Yin Tseng: Low Complexity High Quality Fractional Motion Estimation Algorithm and Architecture Design for H.264/AVC. APCCAS 2006: 578-581
38EEMing-Shuan Lee, Jui-Chin Chu, Jiun-In Guo: Predictive Mode Searching Policy for H.264/AVC Intra Prediction. APCCAS 2006: 764-767
37EEJia-Wei Chen, Chun-Hao Chang, Chien-Chang Lin, Yi-Huan Yang, Jiun-In Guo, Jinn-Shyan Wang: A Condition-based Intra Prediction Algorithm for H.264/AVC. ICME 2006: 1077-1080
36EEWei-Chun Ku, Shu-Hsuan Chou, Jui-Chin Chu, Chih-Heng Kang, Tien-Fu Chen, Jiun-In Guo: Collaborative Multithreading: An Open Scalable Processor Architecture for Embedded Multimedia Applications. ICME 2006: 25-28
35EEYao-Chang Yang, Chien-Chang Lin, Hsui-Cheng Chang, Ching-Lung Su, Jiun-In Guo: A High Throughput VLSI Architecture Design for H.264 Context-Based Adaptive Binary Arithmetic Decoding with Look Ahead Parsing. ICME 2006: 357-360
34EEChih-Da Chien, Keng-Po Lu, Yi-Hung Shih, Jiun-In Guo: A high performance CAVLC encoder design for MPEG-4 AVC/H.264 video coding applications. ISCAS 2006
33EEJia-Wei Chen, Kuan-Hung Chen, Jinn-Shyan Wang, Jiun-In Guo: A performance-aware IP core design for multimode transform coding using scalable-DA algorithm. ISCAS 2006
32EEJui-Chin Chu, Chih-Wen Huang, He-Chun Chen, Keng-Po Lu, Ming-Shuan Lee, Jiun-In Guo, Tien-Fu Chen: Design of customized functional units for the VLIW-based multi-threading processor core targeted at multimedia applications. ISCAS 2006
31EEKuo-Chuan Chao, Kuan-Hung Chen, Yuan-Sun Chu, Jiun-In Guo: Low-power mechanism with power block management. ISCAS 2006
30EEKuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang: A high-performance direct 2-D transform coding IP design for MPEG-4AVC/H.264. IEEE Trans. Circuits Syst. Video Techn. 16(4): 472-483 (2006)
2005
29EEKuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang: An efficient direct 2-D transform coding IP design for MPEG-4 AVC/H.264. ISCAS (5) 2005: 4517-4520
28EEChih-Da Chien, Ho-Chun Chen, Lin-Chieh Huang, Jiun-In Guo: A low-power motion compensation IP core design for MPEG-1/2/4 video decoding. ISCAS (5) 2005: 4542-4545
27EEHsiu-Cheng Chang, Chien-Chang Lin, Jiun-In Guo: A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding. ISCAS (6) 2005: 6110-6113
26EEKuan-Hung Chen, Kuo-Chuan Chao, Jinn-Shyan Wang, Yuan-Sun Chu, Jiun-In Guo: An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design. ISLPED 2005: 155-160
25EEHun-Chen Chen, Jiun-In Guo, Tian-Sheuan Chang, Chein-Wei Jen: A memory-efficient realization of cyclic convolution and its application to discrete cosine transform. IEEE Trans. Circuits Syst. Video Techn. 15(3): 445-453 (2005)
24EEKuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Jia-Wei Chen: An Energy-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms. IEEE Trans. Circuits Syst. Video Techn. 15(5): 704-715 (2005)
23EEHun-Chen Chen, Tian-Sheuan Chang, Jiun-In Guo, Chein-Wei Jen: The Long Length DHT Design with a New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving Partitioning. IEICE Transactions 88-C(5): 1061-1069 (2005)
2004
22 Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh: A power-aware SNR-progressive DCT/IDCT IP core design for multimedia transform coding. ICME 2004: 1683-1686
21 Tai-Lun Chang, Ying-Ming Tsai, Chih-Da Chien, Chien-Chang Lin, Jiun-In Guo: A high-performance MPEG4 bitstream processing core. ICME 2004: 467-470
20 Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Tien-Fu Chen: A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms. ISCAS (2) 2004: 141-144
19 Rei-Chin Ju, Jia-Wei Chen, Jiun-In Guo, Tien-Fu Chen: A parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT. ISCAS (2) 2004: 769-772
18EEChih-Da Chien, Chien-Chang Lin, Jiun-In Guo, Tien-Fu Chen: A power-aware IP core generator for the one-dimensional discrete Fourier transform. ISCAS (3) 2004: 637-640
17EEJiun-In Guo, Rei-Chin Ju, Jia-Wei Chen: An efficient 2-D DCT/IDCT core design using cyclic convolution and adder-based realization. IEEE Trans. Circuits Syst. Video Techn. 14(4): 416-428 (2004)
2003
16EEJiun-In Guo, Jia-Wei Chen, Han-Chen Chen: A new 2-D 8/spl times/8 DCT/IDT core design using group distributed arithmetic. ISCAS (2) 2003: 752-755
15EEHun-Chen Chen, Jiun-In Guo, Chein-Wei Jen: A memory efficient realization of cyclic convolution and its application to discrete cosine transform. ISCAS (4) 2003: 33-36
14EEJiun-In Guo, Chih-Da Chien, Chien-Chang Lin: A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining. ISCAS (5) 2003: 293-296
13EEJiun-In Guo, Jui-Cheng Yen: An Efficient IDCT Processor Design for HDTV Applications. VLSI Signal Processing 33(1-2): 147-155 (2003)
2002
12EEHun-Chen Chen, Jui-Cheng Yen, Jiun-In Guo: Design of a New Cryptography System. IEEE Pacific Rim Conference on Multimedia 2002: 1041-1048
11EEHun-Chen Chen, Jiun-In Guo, Chein-Wei Jen: A new group distributed arithmetic design for the one dimensional discrete Fourier transform. ISCAS (1) 2002: 421-424
10EEJui-Cheng Yen, Jiun-In Guo: Design of a new signal security system. ISCAS (4) 2002: 121-124
9EEJiun-In Guo, Chien-Chang Lin: A new hardware efficient design for the one dimensional discrete Fourier transform. ISCAS (5) 2002: 549-552
8EEJiun-In Guo, Chien-Chang Lin, Chih-Da Chien: A Low-Power Parameterized Hardware Design for the One-Dimensional Discrete Fourier Transform of Variable Lengths. Journal of Circuits, Systems, and Computers 11(4): 405-428 (2002)
2001
7EEJiun-In Guo: A low cost 2-D inverse discrete cosine transform design for image compression. ISCAS (4) 2001: 658-661
6EEJiun-In Guo: A new DA-based array for one dimensional discrete Hartley transform. ISCAS (4) 2001: 662-665
5 Jiun-In Guo, Chih-Chen Li: A generalized architecture for the one-dimensional discrete cosine and sine transforms. IEEE Trans. Circuits Syst. Video Techn. 11(7): 874-881 (2001)
1998
4EEJui-Cheng Yen, Jiun-In Guo, Hun-Chen Chen: A new k-winners-take-all neural network and its array architecture. IEEE Transactions on Neural Networks 9(5): 901-912 (1998)
1994
3 Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen: A General Approach to Design VLSI Arrays for the Multi-dimensional Discrete Hartley Transform. ISCAS 1994: 235-238
1993
2 Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen: A CORDIC-based VLSI Array for Computing 2-D Discrete Hartley Transform. ISCAS 1993: 1571-1574
1 Yu-Sheng Lin, Jiun-In Guo, C. Bernard Shung, Chein-Wei Jen: A Multi-phase Shared Bus Structure for the Fast Fourier Transform. ISCAS 1993: 1575-1578

Coauthor Index

1Chun-Hao Chang [37] [41]
2Hsiu-Cheng Chang [27] [41] [49]
3Hsui-Cheng Chang [35]
4Tai-Lun Chang [21]
5Tian-Sheuan Chang [23] [25]
6Kuo-Chuan Chao [26] [31]
7Ching-Wen Chen [39] [40]
8Han-Chen Chen [16]
9He-Chun Chen [32]
10Ho-Chun Chen [28]
11Hun-Chen Chen [4] [11] [12] [15] [23] [25]
12Jia-Wei Chen [16] [17] [19] [24] [33] [37] [41] [49]
13Kuan-Hung Chen [20] [22] [24] [26] [29] [30] [31] [33] [42]
14Tien-Fu Chen [18] [19] [20] [32] [36] [46]
15Ya-Li Chen [39] [40]
16Yu-Min Chen [42]
17Ching-Hwa Cheng [47] [48]
18Cheng-An Chien [47] [49]
19Chih-Da Chien [8] [14] [18] [21] [28] [34] [43] [45] [47]
20Shu-Hsuan Chou [36] [46]
21Jui-Chin Chu [32] [36] [38] [46] [47]
22Yuan-Hwa Chu [45]
23Yuan-Sun Chu [26] [31] [42]
24Tien-Wei Hsieh [45]
25Chih-Wen Huang [32]
26Lin-Chieh Huang [28]
27Chein-Wei Jen [1] [2] [3] [11] [15] [23] [25]
28Guo-An Jian [43] [44]
29Rei-Chin Ju [17] [19]
30Chih-Heng Kang [36]
31Wei-Chun Ku [36] [46]
32Ming-Shuan Lee [32] [38]
33Chih-Chen Li [5]
34Yao Li [39]
35Chien-Chang Lin [8] [9] [14] [18] [21] [27] [35] [37]
36Chiun-Chau Lin [45]
37Yu-Sheng Lin [1]
38Chi-Min Liu [2] [3]
39Keng-Po Lu [32] [34]
40Yi-Hung Shih [34]
41C. Bernard Shung [1]
42Ching-Lung Su [35] [39] [40] [49]
43Ying-Ming Tsai [21]
44Shau-Yin Tseng [39] [40]
45Chih-Wei Wang [45]
46Chin-Hsien Wang [48]
47Jinn-Shyan Wang [20] [22] [24] [26] [29] [30] [33] [37] [41] [49]
48Wei-Sen Yang [39] [40]
49Yao-Chang Yang [35] [40] [41] [49]
50Yi-Huan Yang [37]
51Chingwei Yeh (Ching-Wei Yeh) [20] [22] [24]
52Jui-Cheng Yen [4] [10] [12] [13]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)