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A. J. van de Goor Vis

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*2006
93EEZaid Al-Ars, Said Hamdioui, A. J. van de Goor: Space of DRAM fault models and corresponding testing. DATE 2006: 1252-1257
92EESaid Hamdioui, Zaid Al-Ars, A. J. van de Goor: Opens and Delay Faults in CMOS RAM Address Decoders. IEEE Trans. Computers 55(12): 1630-1639 (2006)
91EEZaid Al-Ars, Said Hamdioui, A. J. van de Goor, Sultan M. Al-Harbi: Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2989-2996 (2006)
2005
90EEZaid Al-Ars, Said Hamdioui, Georg Mueller, A. J. van de Goor: Framework for Fault Analysis and Test Generation in DRAMs. DATE 2005: 1020-1021
2004
89EEZaid Al-Ars, A. J. van de Goor: Soft Faults and the Importance of Stresses in Memory Testing. DATE 2004: 1084-1091
88EEA. J. van de Goor, Said Hamdioui, Rob Wadsworth: Detecting Faults in the Peripheral Circuits and an Evaluation of SRAM Tests. ITC 2004: 114-123
87EEA. J. van de Goor, Said Hamdioui, Zaid Al-Ars: The Effectiveness of the Scan Test and Its New Variants. MTDT 2004: 26-31
86EEZaid Al-Ars, Martin Herzog, Ivo Schanstra, A. J. van de Goor: Influence of Bit Line Twisting on the Faulty Behavior of DRAMs. MTDT 2004: 32-37
85EESaid Hamdioui, Georgi Gaydadjiev, A. J. van de Goor: The State-of-Art and Future Trends in Testing Embedded Memories. MTDT 2004: 54-59
84EEZaid Al-Ars, Said Hamdioui, A. J. van de Goor: Effects of Bit Line Coupling on the Faulty Behavior of DRAMs. VTS 2004: 117-122
83EEA. J. van de Goor: An Industrial Evaluation of DRAM Tests. IEEE Design & Test of Computers 21(5): 430-440 (2004)
82EESaid Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers: Linked faults in random access memories: concept, fault models, test algorithms, and industrial results. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 737-757 (2004)
81EESaid Hamdioui, Rob Wadsworth, John Delos Reyes, A. J. van de Goor: Memory Fault Modeling Trends: A Case Study. J. Electronic Testing 20(3): 245-255 (2004)
2003
80EEZaid Al-Ars, A. J. van de Goor: Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces. Asian Test Symposium 2003: 24-27
79EESaid Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers: March SL: A Test For All Static Linked Memory Faults. Asian Test Symposium 2003: 372-377
78EEZaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev Richter: Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation. DATE 2003: 10484-10489
77EEIvo Schanstra, A. J. van de Goor: Consequences of RAM Bitline Twisting for Test Coverage. DATE 2003: 11176-11177
76EEZaid Al-Ars, A. J. van de Goor: Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes. MTDT 2003: 27-32
75EEZaid Al-Ars, Said Hamdioui, A. J. van de Goor: A Fault Primitive Based Analysis of Linked Faults in RAMs. MTDT 2003: 33-
74EESaid Hamdioui, A. J. van de Goor, Mike Rodgers: Detecting Intra-Word Faults in Word-Oriented Memories. VTS 2003: 241-247
73EEA. J. van de Goor, Issam B. S. Tlili: A Systematic Method for Modifying March Tests for Bit-Oriented Memories into Tests for Word-Oriented Memories. IEEE Trans. Computers 52(10): 1320-1331 (2003)
72EEZaid Al-Ars, A. J. van de Goor: Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs. IEEE Trans. Computers 52(3): 293-309 (2003)
71EEZaid Al-Ars, A. J. van de Goor: Test generation and optimization for DRAM cell defects using electrical simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1371-1384 (2003)
70EESaid Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers: Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests. J. Electronic Testing 19(2): 195-205 (2003)
2002
69EEZaid Al-Ars, A. J. van de Goor: DRAM Specific Approximation of the Faulty Behavior of Cell Defects. Asian Test Symposium 2002: 98-103
68EEZaid Al-Ars, A. J. van de Goor: Modeling Techniques and Tests for Partial Faults in Memory Devices. DATE 2002: 89-93
67EEA. J. van de Goor, Magdy S. Abadir, Alan Carlin: Minimal Test for Coupling Faults in Word-Oriented Memories. DATE 2002: 944-948
66EEA. J. van de Goor, Ivo Schanstra: Address and Data Scrambling: Causes and Impact on Memory Tests. DELTA 2002: 128-136
65EEM. J. Geuzebroek, J. Th. van der Linden, A. J. van de Goor: Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume. ITC 2002: 138-147
64EESaid Hamdioui, A. J. van de Goor, Mike Rodgers: March SS: A Test for All Static Simple RAM Faults. MTDT 2002: 95-100
63EESaid Hamdioui, Zaid Al-Ars, A. J. van de Goor: Testing Static and Dynamic Faults in Random Access Memories. VTS 2002: 395-400
62EEZaid Al-Ars, A. J. van de Goor: Approximating Infinite Dynamic Behavior for DRAM Cell Defects. VTS 2002: 401-406
61EESaid Hamdioui, A. J. van de Goor: Efficient Tests for Realistic Faults in Dual-Port SRAMs. IEEE Trans. Computers 51(5): 460-473 (2002)
60EESaid Hamdioui, A. J. van de Goor: Thorough testing of any multiport memory with linear tests. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 217-231 (2002)
2001
59EESerge N. Demidenko, A. J. van de Goor, S. Henderson, P. Knoppers: Simulation and Development of Short Transparent Tests for RAM. Asian Test Symposium 2001: 164-
58EEMatthias Klaus, A. J. van de Goor: Tests for Resistive and Capacitive Defects in Address Decoders. Asian Test Symposium 2001: 31-36
57EESaid Hamdioui, A. J. van de Goor, David Eastwick, Mike Rodgers: Detecting Unique Faults in Multi-port SRAMs. Asian Test Symposium 2001: 37-42
56EEZaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev Richter: A Memory Specific Notation for Fault Modeling. Asian Test Symposium 2001: 43-
55EEZaid Al-Ars, A. J. van de Goor: Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs. DATE 2001: 496-503
54 Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev Richter: Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs. ITC 2001: 783-792
53EEZaid Al-Ars, A. J. van de Goor: Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests. MTDT 2001: 59-64
52EESaid Hamdioui, A. J. van de Goor, David Eastwick, Mike Rodgers: Realistic Fault Models and Test Procedures for Multi-Port SRAMs. MTDT 2001: 65-72
2000
51EESaid Hamdioui, A. J. van de Goor: An experimental analysis of spot defects in SRAMs: realistic fault models and tests. Asian Test Symposium 2000: 131-138
50EEZaid Al-Ars, A. J. van de Goor: Impact of memory cell array bridges on the faulty behavior in embedded DRAMs. Asian Test Symposium 2000: 282-289
49 M. J. Geuzebroek, J. Th. van der Linden, A. J. van de Goor: Test point insertion for compact test sets. ITC 2000: 292-301
48 A. J. van de Goor, A. Paalvast: Industrial evaluation of DRAM SIMM tests. ITC 2000: 426-435
47EESaid Hamdioui, A. J. van de Goor, Mike Rodgers, David Eastwick: March Tests for Realistic Faults in Two-Port Memories. MTDT 2000: 73-78
46EEA. J. van de Goor, Zaid Al-Ars: Functional Memory Faults: A Formal Notation and a Taxonomy. VTS 2000: 281-290
45EESaid Hamdioui, A. J. van de Goor: Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy. J. Electronic Testing 16(5): 487-498 (2000)
1999
44EEMario H. Konijnenburg, Hans van der Linden, A. J. van de Goor: Fault (In)Dependent Cost Estimates and Conflict-Directed Backtracking to Guide Sequential Circuit Test Generation. Asian Test Symposium 1999: 185-191
43EEA. J. van de Goor, J. E. Simonse: Defining SRAM Resistive Defects and Their Simulation Stimuli. Asian Test Symposium 1999: 33-40
42EESaid Hamdioui, A. J. van de Goor: March Tests for Word-Oriented Two-Port Memories. Asian Test Symposium 1999: 53-
41EEA. J. van de Goor, J. de Neef: Industrial Evaluation of DRAM Tests. DATE 1999: 623-630
40EEM. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor: Illegal State Space Identification for Sequential Circuit Test Generation. DATE 1999: 741-746
39 Said Hamdioui, A. J. van de Goor: Port interference faults in two-port memories. ITC 1999: 1001-1010
38 M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor: Testability of the Philips 80C51 micro-controller. ITC 1999: 820-829
37 A. J. van de Goor, Ivo Schanstra: Industrial evaluation of stress combinations for march tests applied to SRAMs. ITC 1999: 983-992
36EEDaniel P. Van der Velde, A. J. van de Goor: Designing a Memory Module Tester. MTDT 1999: 91-
1998
35EEJ. Th. van der Linden, M. H. Konijnenburg, A. J. van de Goor: Complete Search in Test Generation for Industrial Circuits with Improved Bus-Conflict Detection. Asian Test Symposium 1998: 212-
34EESaid Hamdioui, A. J. van de Goor: Consequences of Port Restriction on Testing Address Decoders in Two-Port Memories. Asian Test Symposium 1998: 340-347
33EEA. J. van de Goor: Answers to the Key Issues. Asian Test Symposium 1998: 520
32EEA. J. van de Goor, Issam B. S. Tlili: March Tests for Word-Oriented Memories. DATE 1998: 501-
31EESaid Hamdioui, A. J. van de Goor: Consequences of port restrictions on testing two-port memories. ITC 1998: 63-72
30EEIvo Schanstra, Dharmajaya Lukita, A. J. van de Goor, Kees Veelenturf, Paul J. van Wijnen: Semiconductor manufacturing process monitoring using built-in self-test for embedded memories. ITC 1998: 872-
29EEA. J. van de Goor, Said Hamdioui: Fault Models and Tests for Two-Port Memories. VTS 1998: 401-410
1997
28EEA. J. van de Goor, Georgi Gaydadjiev, Vyacheslav N. Yarmolik, V. G. Mikitjuk: March LA: a test for linked memory faults. ED&TC 1997: 627
27 A. J. van de Goor, Mike Lin: The Implementation of Pseudo-Random Memory Tests on Commercial Memory Testers. ITC 1997: 226-235
26 M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor: Sequential Test Generation with Advanced Illegal State Search. ITC 1997: 733-742
25EEA. J. van de Goor, Issam B. S. Tlili: Disturb Neighborhood Pattern Sensitive Fault. VTS 1997: 37-47
1996
24EEA. J. van de Goor, Georgi Gaydadjiev: Realistic Linked Memory Cell Array Faults. Asian Test Symposium 1996: 183-188
23EEJ. Th. van der Linden, M. H. Konijnenburg, A. J. van de Goor: Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors. Asian Test Symposium 1996: 29-33
22 M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor: Accelerated Compact Test Set Generation for Three-State Circuits. ITC 1996: 29-38
21EEA. J. van de Goor, Georgi Gaydadjiev, V. G. Mikitjuk, Vyacheslav N. Yarmolik: March LR: a test for realistic linked faults. VTS 1996: 272-280
1995
20 Jos van Sas, Erik Huyskens, Hans Naert, Fred Schell, A. J. van de Goor: Coping with Re-usability Using Sequential ATPG: A Practical Case Study. ITC 1995: 252-261
19EEM. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor: Compact test sets for industrial circuits. VTS 1995: 358-366
1994
18 A. J. van de Goor, Yervant Zorian, Ivo Schanstra: Functional Tests for Ring-Address SRAM-type FIFOs. EDAC-ETC-EUROASIC 1994: 666
17 Fabian Klass, Michael J. Flynn, A. J. van de Goor: A 16x16-bit Static CMOS Wave-Pipelined Multiplier. ISCAS 1994: 143-146
16 Yervant Zorian, A. J. van de Goor, Ivo Schanstra: An Effective BIST Scheme for Ring-Address Type FIFOs. ITC 1994: 378-387
15 J. Th. van der Linden, M. H. Konijnenburg, A. J. van de Goor: Parallel Pattern Fast Fault Simulation for Three-State Circuits and Bidirectional I/O. ITC 1994: 604-613
14 A. J. van de Goor, B. Smit: Generating March Tests Automatically. ITC 1994: 870-878
13EEFabian Klass, Michael J. Flynn, A. J. van de Goor: Fast multiplication in VLSI using wave pipelining techniques. VLSI Signal Processing 7(3): 233-248 (1994)
1993
12 M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor: Test Pattern Generation with Restrictors. ITC 1993: 598-605
11EEA. J. van de Goor: Using March Tests to Test SRAMs. IEEE Design & Test of Computers 10(1): 8-14 (1993)
1992
10 A. J. van de Goor, Th. J. W. Verhallen: Functional Testing of Current Microprocessors (applied to the Intel i860TM). ITC 1992: 684-695
1991
9 Vlad. Hert, A. J. van de Goor: Truth Table Verification for one-Dimensional CMOS ILA's. Fault-Tolerant Computing Systems 1991: 205-216
8 Gert-Jan Tromp, A. J. van de Goor: Logic Synthesis of 100-percent Testable Logic Networks. ICCD 1991: 428-431
7 A. J. van de Goor, P. C. M. van der Arend, Gert-Jan Tromp: Locating Bridging Faults in Memory Arrays. ITC 1991: 685-694
1990
6 A. J. van de Goor, C. A. Verruijt: An Overview of Deterministic Functional RAM Chip Testing. ACM Comput. Surv. 22(1): 5-33 (1990)
1989
5EEA. J. van de Goor, Henk Corporaal: DOAS: an object oriented architecture supporting secure languages. MICRO 1989: 127-134
1988
4 A. J. van de Goor, A. Moolenaar: UNIX I/O in a Multiprocessor System. USENIX Winter 1988: 251-258
3 Petra De Jong, A. J. van de Goor: Test Pattern Generation for API Faults in RAM. IEEE Trans. Computers 37(11): 1426-1428 (1988)
1986
2 M. D. Janssens, J. K. Annot, A. J. van de Goor: Adapting UNIX for a Multiprocessor Environment. Commun. ACM 29(9): 895-901 (1986)
1 J. K. Annot, M. D. Janssens, A. J. van de Goor: Comments on Morris's Starvation-Free Solution to the Mutual Exclusion Problem. Inf. Process. Lett. 23(2): 91-97 (1986)

Coauthor Index

1Magdy S. Abadir [67]
2Zaid Al-Ars [46] [50] [53] [54] [55] [56] [62] [63] [68] [69] [70] [71] [72] [75] [76] [78] [79] [80] [82] [84] [86] [87] [89] [90] [91] [92] [93]
3Sultan M. Al-Harbi [91]
4J. K. Annot [1] [2]
5P. C. M. van der Arend [7]
6Jens Braun [54] [56] [78]
7Alan Carlin [67]
8Henk Corporaal [5]
9Serge N. Demidenko [59]
10David Eastwick [47] [52] [57]
11Michael J. Flynn [13] [17]
12Georgi Gaydadjiev (Georgi Nedeltchev Gaydadjiev) [21] [24] [28] [85]
13M. J. Geuzebroek [49] [65]
14Said Hamdioui [29] [31] [34] [39] [42] [45] [47] [51] [52] [57] [60] [61] [63] [64] [70] [74] [75] [79] [81] [82] [84] [85] [87] [88] [90] [91] [92] [93]
15S. Henderson [59]
16Vlad. Hert [9]
17Martin Herzog [86]
18Erik Huyskens [20]
19M. D. Janssens [1] [2]
20Petra De Jong [3]
21Fabian Klass [13] [17]
22Matthias Klaus [58]
23P. Knoppers [59]
24Mario H. Konijnenburg (M. H. Konijnenburg) [12] [15] [19] [22] [23] [26] [35] [38] [40] [44]
25Mike Lin [27]
26Hans van der Linden [44]
27J. Th. van der Linden [12] [15] [19] [22] [23] [26] [35] [38] [40] [49] [65]
28Dharmajaya Lukita [30]
29V. G. Mikitjuk [21] [28]
30A. Moolenaar [4]
31Georg Mueller [90]
32Hans Naert [20]
33J. de Neef [41]
34A. Paalvast [48]
35John Delos Reyes [81]
36Detlev Richter [54] [56] [78]
37Mike Rodgers [47] [52] [57] [64] [70] [74] [79] [82]
38Jos van Sas [20]
39Ivo Schanstra [16] [18] [30] [37] [66] [77] [86]
40Fred Schell [20]
41J. E. Simonse [43]
42B. Smit [14]
43Issam B. S. Tlili [25] [32] [73]
44Gert-Jan Tromp [7] [8]
45Kees Veelenturf [30]
46Daniel P. Van der Velde [36]
47Th. J. W. Verhallen [10]
48C. A. Verruijt [6]
49Rob Wadsworth [81] [88]
50Paul J. van Wijnen [30]
51Vyacheslav N. Yarmolik [21] [28]
52Yervant Zorian [16] [18]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)