| 2007 |
|---|
| 10 | EE | Robert Lissel,
Joachim Gerlach,
Robert Bosch GmbH:
Introducing new verification methods into a company's design flow: an industrial user's point of view.
DATE 2007: 689-694 |
| 9 | EE | Djones Lettnin,
Markus Winterholer,
Axel G. Braun,
Joachim Gerlach,
Jürgen Ruf,
Thomas Kropf,
Wolfgang Rosenstiel:
Coverage Driven Verification applied to Embedded Software.
ISVLSI 2007: 159-164 |
| 2006 |
|---|
| 8 | EE | Jan-Hendrik Oetjens,
Joachim Gerlach,
Wolfgang Rosenstiel:
Flexible specification and application of rule-based transformations in an automotive design flow.
DATE Designers' Forum 2006: 82-87 |
| 2004 |
|---|
| 7 | EE | Djones Lettnin,
Axel G. Braun,
Martin Bogdan,
Joachim Gerlach,
Wolfgang Rosenstiel:
Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks.
DATE 2004: 248-255 |
| 6 | EE | Thorsten Schubert,
Jürgen Hanisch,
Joachim Gerlach,
Jens-E. Appell,
Wolfgang Nebel:
Evaluation of a Refinement-Driven SystemC'-Based Design Flow.
DATE 2004: 262-267 |
| 2003 |
|---|
| 5 | | Axel G. Braun,
Jan B. Freuer,
Joachim Gerlach,
Wolfgang Rosenstiel:
Automated Conversion of SystemC Fixed-Point Data Types for Hardware Synthesis.
VLSI-SOC 2003: 55- |
| 2001 |
|---|
| 4 | EE | Jürgen Ruf,
Dirk W. Hoffmann,
Joachim Gerlach,
Thomas Kropf,
Wolfgang Rosenstiel,
Wolfgang Müller:
The simulation semantics of systemC.
DATE 2001: 64-70 |
| 2000 |
|---|
| 3 | EE | Joachim Gerlach,
Wolfgang Rosenstiel:
A Methodology and Tool for Automated Transformational High-Level Design Space Exploration.
ICCD 2000: 545-548 |
| 1998 |
|---|
| 2 | EE | Joachim Gerlach,
Wolfgang Rosenstiel:
A Scalable Methodology for Cost Estimation in a Transformational High-Level Design Space Exploration Environment.
DATE 1998: 226- |
| 1996 |
|---|
| 1 | EE | Heinz-Josef Eikerling,
Wolfram Hardt,
Joachim Gerlach,
Wolfgang Rosenstiel:
A Methodology for Rapid Analysis and Optimization of Embedded Systems.
ECBS 1996: 252-259 |
