Laurent Fesquet

2007
20		Philippe Hoogvorst, Sylvain Guilley, Sumanta Chau, Alin Razafindraibe, Taha Beyrouthy, Laurent Fesquet: A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. ReCoSoC 2007: 15-22
19	EE	N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin: FPGA Architecture for Multi-Style Asynchronous Logic CoRR abs/0710.4711: (2007)
2006
18	EE	Katell Morin-Allory, Laurent Fesquet, Dominique Borrione: Asynchronous Assertion Monitors for multi-Clock Domain System Verification. IEEE International Workshop on Rapid System Prototyping 2006: 98-102
17	EE	Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin: State-holding in Look-Up Tables: application to asynchronous logic. VLSI-SoC 2006: 12-17
2005
16	EE	N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin: FPGA Architecture for Multi-Style Asynchronous Logic. DATE 2005: 32-33
15		Laurent Fesquet, Marc Renaudin: A Programmable Logic Architecture for Prototyping Clockless Circuits. FPL 2005: 293-298
14		Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin: GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. FPL 2005: 299-304
13		Laurent Fesquet, Jerome Quartana, Marc Renaudin: Asynchronous Systems on Programmable Logic. ReCoSoC 2005: 105-112
12	EE	Jerome Quartana, Laurent Fesquet, Marc Renaudin: Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. VLSI-SoC 2005: 195-207
11	EE	Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin: Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. VLSI-SoC 2005: 55-69
2004
10	EE	F. Aeschlimann, Emmanuel Allier, Laurent Fesquet, Marc Renaudin: Asynchronous FIR Filters: Towards a New Digital Processing Chain. ASYNC 2004: 198-206
2003
9	EE	Emmanuel Allier, Gilles Sicard, Laurent Fesquet, Marc Renaudin: A New Class of Asynchronous A/D Converters Based on Time Quantization. ASYNC 2003: 196-205
2002
8	EE	Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana: High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. DATE 2002: 1090
7	EE	Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland: Implementing Asynchronous Circuits on LUT Based FPGAs. FPL 2002: 36-46
6		Anh Vu Dihn Duc, Laurent Fesquet, Marc Renaudin: Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net. IWLS 2002: 191-196
5	EE	Mohammed Es Salhiene, Laurent Fesquet, Marc Renaudin: Dynamic Voltage Scheduling for Real Time Asynchronous Systems. PATMOS 2002: 390-399
4	EE	Emmanuel Allier, Laurent Fesquet, Marc Renaudin, Gilles Sicard: Low-Power Asynchronous A/D Conversion. PATMOS 2002: 81-91
2001
3		Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin: Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. VLSI-SOC 2001: 313-324
1999
2	EE	Wissam Hlayhel, Jacques Collet, Laurent Fesquet: Implementing Snoop-Coherence Protocol for Future SMP Architectures. Euro-Par 1999: 745-752
1998
1	EE	Wissam Hlayhel, Daniel Litaize, Laurent Fesquet, Jacques Collet: Optical versus Electronic Bus for Address-Transactions in Future SMP Architectures. IEEE PACT 1998: 22-29

Coauthor Index

1	F. Aeschlimann	[10]
2	Emmanuel Allier	[4] [9] [10]
3	Arnaud Baixas	[14]
4	Taha Beyrouthy	[20]
5	Dominique Borrione	[18]
6	Vivian Brégier	[11]
7	Sumanta Chau	[20]
8	Jacques Collet	[1] [2]
9	H. Dubreuil	[16] [19]
10	Anh Vu Dihn Duc	[6]
11	Bertrand Folco	[11] [17]
12	Sylvain Guilley	[20]
13	Wissam Hlayhel	[1] [2]
14	Quoc Thai Ho	[7]
15	Philippe Hoogvorst	[20]
16	N. Huot	[16] [19]
17	Daniel Litaize	[1]
18	Katell Morin-Allory	[18]
19	Jerome Quartana	[3] [8] [12] [13] [14]
20	Alin Razafindraibe	[20]
21	Salim Renane	[14]
22	Marc Renaudin	[3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [19]
23	Jean-Baptiste Rigaud	[3] [7] [8]
24	Robin Rolland	[7]
25	Mohammed Es Salhiene	[5]
26	Gilles Sicard	[4] [9]
27	M. Steiner	[17]

Colors in the list of coauthors