João Canas Ferreira Vis

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9EEMiguel L. Silva, João Canas Ferreira: Generation of partial FPGA configurations at run-time. FPL 2008: 367-372
8EEMiguel L. Silva, João Canas Ferreira: Support for partial run-time reconfiguration of platform FPGAs. Journal of Systems Architecture 52(12): 709-726 (2006)
7EEMiguel L. Silva, João Canas Ferreira: Using a Tightly-Coupled Pipeline in Dynamically Reconfigurable Platform FPGAs. DSD 2005: 383-387
6EEJoão Canas Ferreira, Miguel M. Silva: Run-Time Reconfiguration Support for FPGAs with Embedded CPUs: The Hardware Layer. IPDPS 2005
5EEJoão Canas Ferreira, José Silva Matos: A Development Support System for Applications That Use Dynamically Reconfigurable Hardware. FPL 2004: 886-890
4EEJosé Carlos Alves, João Canas Ferreira, C. Albuquerque, José F. Oliveira, J. Soeiro Ferreira, José Silva Matos: FAFNER-Accelerating Nesting Problems with FPGAs. FCCM 1999: 168-
3EEJoão Canas Ferreira, José Silva Matos: A Prototype System for Rapid Application Development using Dynamically Reconfigurable Hardware. FCCM 1998: 280-281
2 José Silva Matos, João Canas Ferreira, Ana C. Leão, José Machado da Silva: An Approach to Testability Improvement of Mixed-Signal Boards. ISCAS 1994: 161-164
1 José Silva Matos, Ana C. Leão, João Canas Ferreira: Control and Observation of Analog Nodes in Mixed-Signal Boards. ITC 1993: 323-331

Coauthor Index

1C. Albuquerque [4]
2José Carlos Alves [4]
3J. Soeiro Ferreira [4]
4Ana C. Leão [1] [2]
5José Silva Matos [1] [2] [3] [4] [5]
6José F. Oliveira [4]
7José Machado da Silva [2]
8Miguel L. Silva [7] [8] [9]
9Miguel M. Silva [6]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)