Wolfgang Ecker Vis

*	2009
30	EE	Wolfgang Ecker, Stefan Heinen, Michael Velten: Using a dataflow abstracted virtual prototype for HdS-design. ASP-DAC 2009: 293-300
	2008
29	EE	Wido Kruijtzer, Pieter van der Wolf, Erwin A. de Kock, Jan Stuyt, Wolfgang Ecker, Albrecht Mayer, Serge Hustin, Christophe Amerijckx, Serge de Paoli, Emmanuel Vaumorin: Industrial IP Integration Flows based on IP-XACT Standards. DATE 2008: 32-37
	2007
28	EE	Wolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, Michael Hull: Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance. DATE 2007: 767-772
27	EE	Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Michael Hull: Interactive presentation: Implementation of a transaction level assertion framework in SystemC. DATE 2007: 894-899
26	EE	Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten: Requirements and Concepts for Transaction Level Assertion Refinement. IESS 2007: 1-14
	2006
25	EE	Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten: Case Study on Transaction Level Modeling. FDL 2006: 209-215
24	EE	Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Jacob Smit: IP Library For Temporal SystemC Assertions. FDL 2006: 301-309
23	EE	Wolfgang Ecker, Volkan Esen, Michael Hull, Thomas Steininger, Michael Velten: Requirements and Concepts for Transaction Level Assertions. ICCD 2006
22	EE	Wolfgang Ecker, Volkan Esen, Michael Hull: Execution semantics and formalisms for multi-abstraction TLM assertions. MEMOCODE 2006: 93-102
	2005
21		Wolfgang Ecker, Lothar Schrader: Evolution of Paradigm Shifts in the Automated Design Process of Digital Circuits. GI Jahrestagung (1) 2005: 313
	2004
20	EE	P. Jensen, Wolfgang Ecker, T. Kruse, Martin Zambaldi: SystemVerilog: Interface Based Design. FDL 2004: 505-518
19	EE	Martin Zambaldi, Wolfgang Ecker: Extending the RASSP model for Verification. FDL 2004: 536-544
18	EE	Martin Zambaldi, Wolfgang Ecker, T. Kruse, W. Müller: The Formal Simulation Semantics of SystemVerilog. FDL 2004: 568-578
17	EE	Wolfgang Ecker, Volkan Esen, Thomas Steininger, Martin Zambaldi: Memory Models for the Formal Verification of Assembler Code Using Bounded Model Checking. ISORC 2004: 129-135
16	EE	Martin Zambaldi, Wolfgang Ecker: How to Bridge the Gap Between Simulationand Test. ITC 2004: 1091-1099
15	EE	Martin Zambaldi, Wolfgang Ecker, Renate Henftling, Matthias Bauer: A Layered Adaptive Verification Platform for Simulation, Test, and Emulation. IEEE Design & Test of Computers 21(6): 464-471 (2004)
	2003
14	EE	Renate Henftling, Andreas Zinn, Matthias Bauer, Martin Zambaldi, Wolfgang Ecker: Re-use-centric architecture for a fully accelerated testbench environment. DAC 2003: 372-375
13	EE	Renate Henftling, Andreas Zinn, Matthias Bauer, Wolfgang Ecker, Martin Zambaldi: Platform-Based Testbench Generation. DATE 2003: 11038-11045
12	EE	Renate Henftling, Wolfgang Ecker, Andreas Zinn, Martin Zambaldi, Matthias Bauer: An Approach for Mixed Coarse-Granular and Fine-Granular Re-Configurable Architectures. IPDPS 2003: 187
	1999
11	EE	Matthias Bauer, Wolfgang Ecker, Renate Henftling, Andreas Zinn: A Method for Accelerating Test Environments. EUROMICRO 1999: 1477-1480
	1997
10	EE	Matthias Bauer, Wolfgang Ecker: Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach. DAC 1997: 774-779
9	EE	Michael Mrva, Mike Heuchling, Wolfgang Ecker: The Shall-Prototype-Test Development model. ECBS 1997: 385-391
	1996
8	EE	Manfred Selz, Wolfgang Ecker, Eugenio Villar: VHDL synthesis description portability: The need for Level synthesis subsets. Journal of Systems Architecture 42(2): 105-116 (1996)
7	EE	Wolfgang Ecker: Verification methods for VHDL RTL-subroutines. Journal of Systems Architecture 42(2): 117-128 (1996)
	1995
6	EE	Wolfgang Ecker: Semi-dynamic scheduling of synchronization-mechanisms. EURO-DAC 1995: 374-379
5	EE	Wolfgang Ecker, Manfred Huber: VHDL-based communication and synchronization synthesis. EURO-DAC 1995: 458-462
4	EE	Wolfgang Ecker: A classification of design steps and their verification. EURO-DAC 1995: 536-541
	1994
3	EE	Wolfgang Ecker, Manfred Glesner, Andreas Vombach: Protocol merging: a VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations. EURO-DAC 1994: 624-629
	1993
2		Wolfgang Ecker, Sabine März: System-Level Specification and Design Using VHDL: A Case Study. CHDL 1993: 505-522
1	EE	Wolfgang Ecker, M. Hofmeister: State look ahead technique for cycle optimization of interacting finite state Moore machines. ICCAD 1993: 392-397

Coauthor Index

1	Christophe Amerijckx	[29]
2	Matthias Bauer	[10] [11] [12] [13] [14] [15]
3	Volkan Esen	[17] [22] [23] [24] [25] [26] [27] [28]
4	Manfred Glesner	[3]
5	Stefan Heinen	[30]
6	Renate Henftling	[11] [12] [13] [14] [15]
7	Mike Heuchling	[9]
8	M. Hofmeister	[1]
9	Manfred Huber	[5]
10	Michael Hull	[22] [23] [27] [28]
11	Serge Hustin	[29]
12	P. Jensen	[20]
13	Erwin A. de Kock	[29]
14	Wido Kruijtzer (W. M. Kruijtzer)	[29]
15	T. Kruse	[18] [20]
16	Sabine März	[2]
17	Albrecht Mayer	[29]
18	Michael Mrva	[9]
19	W. Müller	[18]
20	Serge de Paoli	[29]
21	Lars Schönberg	[28]
22	Lothar Schrader	[21]
23	Manfred Selz	[8]
24	Jacob Smit	[24]
25	Thomas Steininger	[17] [23] [24] [25] [26] [27] [28]
26	Jan Stuyt	[29]
27	Emmanuel Vaumorin	[29]
28	Michael Velten	[23] [24] [25] [26] [27] [28] [30]
29	Eugenio Villar	[8]
30	Andreas Vombach	[3]
31	Pieter van der Wolf	[29]
32	Martin Zambaldi	[12] [13] [14] [15] [16] [17] [18] [19] [20]
33	Andreas Zinn	[11] [12] [13] [14]

Colors in the list of coauthors