| |
| * | 1995 | |
|---|---|---|
| 2 | EE | Siamak Arya, Howard Sachs, Sreeram Duvvuru: An architecture for high instruction level parallelism. HICSS (1) 1995: 153-162 |
| 1 | EE | Sreeram Duvvuru, Siamak Arya: Evaluation of a branch target address cache. HICSS (1) 1995: 173-180 |
| 1 | Siamak Arya | [1] [2] |
| 2 | Howard Sachs | [2] |