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Shantanu Dutt Vis

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*2009
56EEShantanu Dutt, Yang Dai, Huan Ren, Joel Fontanarosa: Selection of Multiple SNPs in Case-Control Association Study Using a Discretized Network Flow Approach. BICoB 2009: 211-223
55EEShantanu Dutt, Li Li: Trust-Based Design and Check of FPGA Circuits Using Two-Level Randomized ECC Structures. TRETS 2(1): (2009)
2008
54EEHuan Ren, Shantanu Dutt: Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure. ICCAD 2008: 93-100
53EEShantanu Dutt, Vinay Verma, Vishal Suthar: Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 309-326 (2008)
2007
52EEHuan Ren, Shantanu Dutt: Constraint satisfaction in incremental placement with application to performance optimization under power constraints. ICCD 2007: 251-258
51EENihar R. Mahapatra, Shantanu Dutt: An efficient delay-optimal distributed termination detection algorithm. J. Parallel Distrib. Comput. 67(10): 1047-1066 (2007)
2006
50EEVishal Suthar, Shantanu Dutt: Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults. DATE 2006: 1165-1170
49EEShantanu Dutt, Hasan Arslan: Efficient timing-driven incremental routing for VLSI circuits using DFS and localized slack-satisfaction computations. DATE 2006: 768-773
48EEFederico Rota, Shantanu Dutt, Sahithi Krishna: Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream. DFT 2006: 507-515
47EEShantanu Dutt, Huan Ren, Fenghua Yuan, Vishal Suthar: A network-flow approach to timing-driven incremental placement for ASICs. ICCAD 2006: 375-382
46EEVishal Suthar, Shantanu Dutt: Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions. VTS 2006: 36-43
2005
45EEVishal Suthar, Shantanu Dutt: High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping. ACM Great Lakes Symposium on VLSI 2005: 78-83
2004
44EEHasan Arslan, Shantanu Dutt: An effective hop-based detailed router for FPGAs for optimizing track usage and circuit performance. ACM Great Lakes Symposium on VLSI 2004: 208-213
43EEVinay Verma, Shantanu Dutt, Vishal Suthar: Efficient on-line testing of FPGAs with provable diagnosabilities. DAC 2004: 498-503
42EEVinay Verma, Shantanu Dutt: Roving testing using new built-in-self-tester designs for FPGAs. FPGA 2004: 257
41EEHasan Arslan, Shantanu Dutt: A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits. ICCD 2004: 86-92
40EENihar R. Mahapatra, Shantanu Dutt: Adaptive Quality Equalizing: High-performance load balancing for parallel branch-and-bound across applications and computing systems. Parallel Computing 30(5-6): 867-881 (2004)
2003
39EEHasan Arslan, Shantanu Dutt: ROAD : An Order-Impervious Optimal Detailed Router for FPGAs. ICCD 2003: 350-
2002
38EEKe Zhong, Shantanu Dutt: Algorithms for simultaneous satisfaction of multiple constraints and objective optimization in a placement flow with application to congestion control. DAC 2002: 854-859
37EEShantanu Dutt, Wenyong Deng: Cluster-aware iterative improvement techniques for partitioning large VLSI circuits. ACM Trans. Design Autom. Electr. Syst. 7(1): 91-121 (2002)
36EEShantanu Dutt, Vinay Verma, Hasan Arslan: A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs. ACM Trans. Design Autom. Electr. Syst. 7(4): 664-693 (2002)
2001
35EEVinay Verma, Shantanu Dutt: A Search-Based Bump-and-Refit Approach to Incremental Routing for ECO Applications in FPGAs. ICCAD 2001: 144-
34EENihar R. Mahapatra, Shantanu Dutt: Hardware-Efficient and Highly Reconfigurable 4- and 2-Track Fault-Tolerant Designs for Mesh-Connected Arrays. J. Parallel Distrib. Comput. 61(10): 1391-1411 (2001)
2000
33 Ke Zhong, Shantanu Dutt: Effective Partition-Driven Placement with Simultaneous Level Processing and a Global Net Views. ICCAD 2000: 254-259
32EEShantanu Dutt, Wenyong Deng: Probability-based approaches to VLSI circuit partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 534-549 (2000)
31 Nihar R. Mahapatra, Shantanu Dutt: Random Seeking: A General, Efficient, and Informed Randomized Scheme for Dynamic Load Balancing. Int. J. Found. Comput. Sci. 11(2): 231-246 (2000)
1999
30EENihar R. Mahapatra, Shantanu Dutt: Efficient Network-Flow Based Techniques for Dynamic Fault Reconfiguration in FPGAs. FTCS 1999: 122-129
29EEShantanu Dutt, Vimalvel Shanmugavel, Steven Trimberger: Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays. ICCAD 1999: 173-177
28EEShantanu Dutt, Hasan Arslan, Halim Theny: Partitioning using second-order information and stochastic-gainfunctions. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 421-435 (1999)
1998
27EENihar R. Mahapatra, Shantanu Dutt: Adaptive Quality Equalizing: High-Performance Load Balancing for Parallel Branch-and-Bound Across Applications and Computing Systems. IPPS/SPDP 1998: 796-800
26EEShantanu Dutt, Halim Theny: Partitioning using second-order information and stochastic-gain functions. ISPD 1998: 112-117
25 Fran Hanchek, Shantanu Dutt: Methodologies for Tolerating Cell and Interconnect Faults in FPGAs. IEEE Trans. Computers 47(1): 15-33 (1998)
1997
24EEShantanu Dutt, Halim Theny: Partitioning around roadblocks: tackling constraints with intermediate relaxations. ICCAD 1997: 350-355
23 Shantanu Dutt, Nihar R. Mahapatra: Node-Covering, Error-Correcting Codes and Multiprocessors with Very High Average Fault Tolerance. IEEE Trans. Computers 46(9): 997-1015 (1997)
22EENihar R. Mahapatra, Shantanu Dutt: Scalable Global and Local Hashing Strategies for Duplicate Pruning in Parallel A* Graph Search. IEEE Trans. Parallel Distrib. Syst. 8(7): 738-756 (1997)
21EEShantanu Dutt, Fran Hanchek: REMOD: a new methodology for designing fault-tolerant arithmetic circuits. IEEE Trans. VLSI Syst. 5(1): 34-56 (1997)
1996
20EEShantanu Dutt, Wenyong Deng: A Probability-Based Approach to VLSI Circuit Partitioning. DAC 1996: 100-105
19 Nihar R. Mahapatra, Shantanu Dutt: Hardware-Efficient and Highly-Reconfigurable 4- and 2-Track: Fault-Tolerant Designs for Mesh-Connected Multicomputers. FTCS 1996: 272-281
18EEShantanu Dutt, Wenyong Deng: VLSI circuit partitioning by cluster-removal using iterative improvement techniques. ICCAD 1996: 194-200
17EEFran Hancheck, Shantanu Dutt: Design Methodologies for Tolerating Cell and Interconnect Faults in FPGAs. ICCD 1996: 326-331
16EENihar R. Mahapatra, Shantanu Dutt: Random Seeking: A General, Efficient, and Informed Randomized Scheme for Dynamic Load Balancing. IPPS 1996: 881-885
15EEShantanu Dutt, Nam Trinh: Are There Advantages to High-Dimension Architectures? Analysis of k-ary n-Cubes for the Class of Parallel Divide-and-Conquer Algorithms. International Conference on Supercomputing 1996: 398-406
14EEFran Hanchek, Shantanu Dutt: Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs. VLSI Design 1996: 225-229
13 Shantanu Dutt, Fikri T. Assaad: Mantissa-Preserving Operations and Robust Algorithm-Based Fault Tolerance for Matrix Computations. IEEE Trans. Computers 45(4): 408-424 (1996)
1995
12 Shantanu Dutt, Nihar R. Mahapatra: Node Covering, Error Correcting Codes and Multiprocessors with Very High Average Fault Tolerance. FTCS 1995: 320-329
1994
11 Shantanu Dutt, Nihar R. Mahapatra: Scalable Load Balancing Strategies for Parallel A* Algorithms. J. Parallel Distrib. Comput. 22(3): 488-505 (1994)
1993
10EEShantanu Dutt: New faster Kernighan-Lin-type graph-partitioning algorithms. ICCAD 1993: 370-377
9 Shantanu Dutt, Nihar R. Mahapatra: Parallel A* Algorithms and Their Performance on Hypercube Multiprocessors. IPPS 1993: 797-803
8 Nihar R. Mahapatra, Shantanu Dutt: Scalable Duplicate Pruning Strategies for Parallel A* Graph Search. SPDP 1993: 290-297
7 Shantanu Dutt: Fast Polylog-Time Reconfiguration of Structurally Fault-Tolerant Multiprocessors. SPDP 1993: 762-770
1992
6 Fikri T. Assaad, Shantanu Dutt: More Robust Tests in Algorithm-Based Fault-Tolerant Matrix Multiplication. FTCS 1992: 430-439
5 Shantanu Dutt, John P. Hayes: Some Practical Issues in the Design of Fault-Tolerant Multiprocessors. IEEE Trans. Computers 41(5): 588-598 (1992)
1991
4 Shantanu Dutt, John P. Hayes: Some Practical Issues in the Design of Fault-Tolerant Multiprocessors. FTCS 1991: 292-299
3 Shantanu Dutt, John P. Hayes: Subcube Allocation in Hypercube Computers. IEEE Trans. Computers 40(3): 341-352 (1991)
2 Shantanu Dutt, John P. Hayes: Designing Fault-Tolerant System Using Automorphisms. J. Parallel Distrib. Comput. 12(3): 249-268 (1991)
1990
1 Shantanu Dutt, John P. Hayes: On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures. IEEE Trans. Computers 39(4): 490-503 (1990)

Coauthor Index

1Hasan Arslan [28] [36] [39] [41] [44] [49]
2Fikri T. Assaad [6] [13]
3Yang Dai [56]
4Wenyong Deng [18] [20] [32] [37]
5Joel Fontanarosa [56]
6Fran Hancheck [17]
7Fran Hanchek [14] [21] [25]
8John P. Hayes [1] [2] [3] [4] [5]
9Sahithi Krishna [48]
10Li Li [55]
11Nihar R. Mahapatra [8] [9] [11] [12] [16] [19] [22] [23] [27] [30] [31] [34] [40] [51]
12Huan Ren [47] [52] [54] [56]
13Federico Rota [48]
14Vimalvel Shanmugavel [29]
15Vishal Suthar [43] [45] [46] [47] [50] [53]
16Halim Theny [24] [26] [28]
17Steven Trimberger [29]
18Nam Trinh [15]
19Vinay Verma [35] [36] [42] [43] [53]
20Fenghua Yuan [47]
21Ke Zhong [33] [38]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)