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Rolf Drechsler Vis

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*2009
248EEDaniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler: Contradictory antecedent debugging in bounded model checking. ACM Great Lakes Symposium on VLSI 2009: 173-176
247EEGörschwin Fey, André Sülflow, Rolf Drechsler: Computing bounds for fault tolerance using formal techniques. DAC 2009: 190-195
246EERobert Wille, Rolf Drechsler: BDD-based synthesis of reversible logic for large functions. DAC 2009: 270-275
245EEUlrich Kühne, Daniel Große, Rolf Drechsler: Property analysis and design understanding. DATE 2009: 1246-1249
244EERobert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler: Debugging of Toffoli networks. DATE 2009: 1284-1289
243EEAndré Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler: Increasing the accuracy of SAT-based debugging. DATE 2009: 1326-1331
242EEChristian Genz, Rolf Drechsler: Overcoming limitations of the SystemC data introspection. DATE 2009: 590-593
241EEDaniel Tille, Rolf Drechsler: A fast untestability proof for SAT-based ATPG. DDECS 2009: 38-43
240EERobert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler: Reversible Logic Synthesis with Output Permutation. VLSI Design 2009: 189-194
239EERolf Drechsler, Tommi A. Junttila, Ilkka Niemelä: Non-Clausal SAT and ATPG. Handbook of Satisfiability 2009: 655-693
238EERüdiger Ebendt, Rolf Drechsler: Weighted A* search - unifying view and application. Artif. Intell. 173(14): 1310-1342 (2009)
2008
237 Mario Giacobini, Anthony Brabazon, Stefano Cagnoni, Gianni Di Caro, Rolf Drechsler, Anikó Ekárt, Anna Esparcia-Alcázar, Muddassar Farooq, Andreas Fink, Jon McCormack, Michael O'Neill, Juan Romero, Franz Rothlauf, Giovanni Squillero, Sima Uyar, Shengxiang Yang: Applications of Evolutionary Computing, EvoWorkshops 2008: EvoCOMNET, EvoFIN, EvoHOT, EvoIASP, EvoMUSART, EvoNUM, EvoSTOC, and EvoTransLog, Naples, Italy, March 26-28, 2008. Proceedings Springer 2008
236EEAndré Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler: Using unsatisfiable cores to debug multiple design errors. ACM Great Lakes Symposium on VLSI 2008: 77-82
235EESujan Pandey, Rolf Drechsler: Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival. ASP-DAC 2008: 601-606
234EESujan Pandey, Rolf Drechsler: Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs. DATE 2008: 206-211
233EEFrank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke: Automatic Generation of Complex Properties for Hardware Designs. DATE 2008: 545-548
232EEDaniel Tille, Rolf Drechsler: Incremental SAT Instance Generation for SAT-based ATPG. DDECS 2008: 68-73
231EERobert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler: Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. DSD 2008: 542-549
230EEDaniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler: Contradiction Analysis for Constraint-based Random Simulation. FDL 2008: 130-135
229EESujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner: Process variations aware robust on-chip bus architecture synthesis for MPSoCs. ISCAS 2008: 2989-2992
228EEDaniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. ISMVL 2008: 214-219
227EERobert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler: RevLib: An Online Resource for Reversible Functions and Reversible Circuits. ISMVL 2008: 220-225
226EEDoina Logofatu, Rolf Drechsler: Comparative Study by Solving the Test Compaction Problem. ISMVL 2008: 44-49
225EEStephan Eggersglüß, Rolf Drechsler: On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults. ISMVL 2008: 94-99
224EEMurthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler: Adaptive Branch and Bound Using SAT to Estimate False Crosstalk. ISQED 2008: 508-513
223EEGörschwin Fey, Rolf Drechsler: A Basis for Formal Robustness Checking. ISQED 2008: 784-789
222EERobert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler: Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability. ISVLSI 2008: 411-416
221EEGörschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler: Automatic Fault Localization for Property Checking. IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1138-1149 (2008)
220EEAnna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa: Logic Minimization and Testability of 2-SPP Networks. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1190-1202 (2008)
219EEDaniel Große, Ulrich Kühne, Rolf Drechsler: Analyzing Functional Coverage in Bounded Model Checking. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1305-1314 (2008)
218EERolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille: On Acceleration of SAT-Based ATPG for Industrial Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1329-1333 (2008)
217EEGörschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler: On the construction of small fully testable circuits with low depth. Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 263-269 (2008)
216EESebastian Kinder, Rolf Drechsler: Modeling and proving functional completeness in formal verification of counting heads. STTT 10(6): 521-534 (2008)
2007
215 Mario Giacobini, Anthony Brabazon, Stefano Cagnoni, Gianni Di Caro, Rolf Drechsler, Muddassar Farooq, Andreas Fink, Evelyne Lutton, Penousal Machado, Stefan Minner, Michael O'Neill, Juan Romero, Franz Rothlauf, Giovanni Squillero, Hideyuki Takagi, Sima Uyar, Shengxiang Yang: Applications of Evolutinary Computing, EvoWorkshops 2007: EvoCoMnet, EvoFIN, EvoIASP,EvoINTERACTION, EvoMUSART, EvoSTOC and EvoTransLog, Valencia, Spain, April11-13, 2007, Proceedings. Springer 2007
214EEDaniel Große, Rüdiger Ebendt, Rolf Drechsler: Improvements for constraint solving in the systemc verification library. ACM Great Lakes Symposium on VLSI 2007: 493-496
213EEDaniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler: Exact sat-based toffoli network synthesis. ACM Great Lakes Symposium on VLSI 2007: 96-101
212EEDaniel Große, Ulrich Kühne, Rolf Drechsler: Estimating functional coverage in bounded model checking. DATE 2007: 1176-1181
211 Daniel Tille, Görschwin Fey, Rolf Drechsler: Instance Generation for SAT-based ATPG. DDECS 2007: 153-156
210EESebastian Kinder, Rolf Drechsler: Proving Completeness of Properties in Formal Verification of Counting Heads for Railways. DSD 2007: 396-403
209EEGörschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler: On the Construction of Small Fully Testable Circuits with Low Depth. DSD 2007: 563-569
208EEFrank Rogin, Christian Genz, Rolf Drechsler, Steffen Rülke: An Integrated SystemC Debugging Environment. FDL 2007: 140-145
207EEDaniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler: Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques. FDL 2007: 146-151
206 Rolf Drechsler, Andreas Breiter: Hardware Project Management - What we Can Learn from the Software Development Process for Hardware Design?. ICSOFT (SE) 2007: 409-416
205EEStephan Eggersglüß, Görschwin Fey, Rolf Drechsler: SAT-based ATPG for Path Delay Faults in Sequential Circuits. ISCAS 2007: 3671-3674
204EEChristian Genz, Rolf Drechsler, Gerhard Angst, Lothar Linhard: Visualization of SystemC Designs. ISCAS 2007: 413-416
203EEAndré Sülflow, Rolf Drechsler: Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC. ISMVL 2007: 42
202EEMahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler: Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL. ISMVL 2007: 50
201EEStephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: Experimental Studies on SAT-Based ATPG for Gate Delay Faults. ISMVL 2007: 6
200EEUlrich Kühne, Daniel Große, Rolf Drechsler: Improving the Quality of Bounded Model Checking by Means of Coverage Estimation. ISVLSI 2007: 165-170
199EEStephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. MEMOCODE 2007: 181-187
198EEGörschwin Fey, Tim Warode, Rolf Drechsler: Reusing Learned Information in SAT-based ATPG. VLSI Design 2007: 69-76
197EESujan Pandey, Christian Genz, Rolf Drechsler: Co-synthesis of custom on-chip bus and memory for MPSoC architectures. VLSI-SoC 2007: 304-307
196EERobert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler: SWORD: A SAT like prover using word level information. VLSI-SoC 2007: 88-93
195EESabine Glesner, Jens Knoop, Rolf Drechsler: Preface. Electr. Notes Theor. Comput. Sci. 190(4): 1-2 (2007)
194EEBeate Muranko, Rolf Drechsler: Technische Dokumentation von Soft- und Hardware in Eingebetteten Systemen (Technical Documentation of Soft- and Hardware in Embedded Systems). it - Information Technology 49(2): 110- (2007)
2006
193 Franz Rothlauf, Jürgen Branke, Stefano Cagnoni, Ernesto Costa, Carlos Cotta, Rolf Drechsler, Evelyne Lutton, Penousal Machado, Jason H. Moore, Juan Romero, George D. Smith, Giovanni Squillero, Hideyuki Takagi: Applications of Evolutionary Computing, EvoWorkshops 2006: EvoBIO, EvoCOMNET, EvoHOT, EvoIASP, EvoINTERACTION, EvoMUSART, and EvoSTOC, Budapest, Hungary, April 10-12, 2006, Proceedings Springer 2006
192EEDaniel Große, Ulrich Kühne, Rolf Drechsler: HW/SW co-verification of embedded systems using bounded model checking. ACM Great Lakes Symposium on VLSI 2006: 43-48
191EEGörschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler: On the relation between simulation-based and SAT-based diagnosis. DATE 2006: 1139-1144
190EEGörschwin Fey, Daniel Große, Rolf Drechsler: Avoiding false negatives in formal verification for protocol-driven blocks. DATE 2006: 1225-1226
189EEAnna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa: Efficient minimization of fully testable 2-SPP networks. DATE 2006: 1300-1305
188EEAndré Sülflow, Nicole Drechsler, Rolf Drechsler: Robust Multi-Objective Optimization in High Dimensional Spaces. EMO 2006: 715-726
187EEDoina Logofatu, Rolf Drechsler: Efficient Evolutionary Approaches for the Data Ordering Problem with Inversion. EvoWorkshops 2006: 320-331
186EEStefan Staber, Görschwin Fey, Roderick Bloem, Rolf Drechsler: Automatic Fault Localization for Property Checking. Haifa Verification Conference 2006: 50-64
185EESean Safarpour, Andreas G. Veneris, Rolf Drechsler: Integrating observability don't cares in all-solution SAT solvers. ISCAS 2006
184EERüdiger Ebendt, Rolf Drechsler: On the sensitivity of BDDs with respect to path-related objective functions. ISCAS 2006
183EEGörschwin Fey, Junhao Shi, Rolf Drechsler: Efficiency of Multi-Valued Encoding in SAT-based ATPG. ISMVL 2006: 25
182EEChristian Genz, Rolf Drechsler: System Exploration of SystemC Designs. ISVLSI 2006: 335-342
181EERüdiger Ebendt, Rolf Drechsler: A Framework for Quasi-exact Optimization Using Relaxed Best-First Search. KI 2006: 331-345
180EERolf Drechsler, Görschwin Fey: Automatic Test Pattern Generation. SFM 2006: 30-55
179EERolf Drechsler, Görschwin Fey, Sebastian Kinder: An Integrated Approach for Combining BDD and SAT Provers. VLSI Design 2006: 237-242
178EEBeate Muranko, Rolf Drechsler: Technical Documentation of Software and Hardware in Embedded Systems. VLSI-SoC 2006: 261-266
177EEGörschwin Fey, Rolf Drechsler: Minimizing the number of paths in BDDs: Theory and algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 4-11 (2006)
176EEValentina Ciriani, Anna Bernasconi, Rolf Drechsler: Testability of SPP Three-Level Logic Networks in Static Fault Models. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2241-2248 (2006)
175EERüdiger Ebendt, Rolf Drechsler: Effect of improved lower bounds in dynamic BDD reordering. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 902-909 (2006)
2005
174 Franz Rothlauf, Jürgen Branke, Stefano Cagnoni, David W. Corne, Rolf Drechsler, Yaochu Jin, Penousal Machado, Elena Marchiori, Juan Romero, George D. Smith, Giovanni Squillero: Applications of Evolutionary Computing, EvoWorkshops 2005: EvoBIO, EvoCOMNET, EvoHOT, EvoIASP, EvoMUSART, and EvoSTOC, Lausanne, Switzerland, March 30 - April 1, 2005, Proceedings Springer 2005
173EESean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler: Utilizing don't care states in SAT-based bounded sequential problems. ACM Great Lakes Symposium on VLSI 2005: 264-269
172EEJunhao Shi, Görschwin Fey, Rolf Drechsler: Bridging fault testability of BDD circuits. ASP-DAC 2005: 188-191
171EERüdiger Ebendt, Rolf Drechsler: Lower bounds for dynamic BDD reordering. ASP-DAC 2005: 579-582
170EEDaniel Große, Rolf Drechsler: Acceleration of SAT-Based Iterative Property Checking. CHARME 2005: 349-353
169 Daniel Große, Ulrich Kühne, Rolf Drechsler: Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors. GI Jahrestagung (1) 2005: 308-312
168 Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler: Post-verification debugging of hierarchical designs. ICCAD 2005: 871-876
167EERolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große: SyCE: An Integrated Environment for System Design in SystemC. IEEE International Workshop on Rapid System Prototyping 2005: 258-260
166EEDaniel Große, Rolf Drechsler: CheckSyC: an efficient property checker for RTL SystemC designs. ISCAS (4) 2005: 4167-4170
165EESebastian Kinder, Görschwin Fey, Rolf Drechsler: Controlling the Memory During Manipulation of Word-Level Decision Diagrams. ISMVL 2005: 250-255
164EEJunhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits. ISVLSI 2005: 212-217
163EERüdiger Ebendt, Rolf Drechsler: Quasi-Exact BDD Minimization Using Relaxed Best-First Search. ISVLSI 2005: 59-64
162EEDaniel Große, Ulrich Kühne, Rolf Drechsler: HW/SW Co-Verification of a RISC CPU using Bounded Model Checking. MTV 2005: 133-137
161EEMoayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler: Post-Verification Debugging of Hierarchical Designs. MTV 2005: 42-47
160EERüdiger Ebendt, Rolf Drechsler: Exact BDD Minimization for Path-Related Objective Functions. VLSI-SoC 2005: 299-315
159EERüdiger Ebendt, Wolfgang Günther, Rolf Drechsler: Combining ordered best-first search with branch and bound for exact BDD minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1515-1529 (2005)
2004
158 Günther R. Raidl, Stefano Cagnoni, Jürgen Branke, David Corne, Rolf Drechsler, Yaochu Jin, Colin G. Johnson, Penousal Machado, Elena Marchiori, Franz Rothlauf, George D. Smith, Giovanni Squillero: Applications of Evolutionary Computing, EvoWorkshops 2004: EvoBIO, EvoCOMNET, EvoHOT, EvoIASP, EvoMUSART, and EvoSTOC, Coimbra, Portugal, April 5-7, 2004, Proceedings Springer 2004
157EEGörschwin Fey, Rolf Drechsler: Improving simulation-based verification by means of formal methods. ASP-DAC 2004: 640-643
156EERüdiger Ebendt, Wolfgang Günther, Rolf Drechsler: Minimization of the expected path length in BDDs based on local changes. ASP-DAC 2004: 865-870
155EERüdiger Ebendt, Wolfgang Günther, Rolf Drechsler: Combining ordered best-first search with branch and bound for exact BDD minimization. ASP-DAC 2004: 875-878
154EESean Safarpour, Andreas G. Veneris, Rolf Drechsler, Joanne Lee: Managing Don't Cares in Boolean Satisfiability. DATE 2004: 260-265
153EEGörschwin Fey, Junhao Shi, Rolf Drechsler: BDD Circuit Optimization for Path Delay Fault Testability. DSD 2004: 168-172
152EENicole Drechsler, Mario Hilgemeier, Görschwin Fey, Rolf Drechsler: Disjoint Sum of Product Minimization by Evolutionary Algorithms. EvoWorkshops 2004: 198-207
151EEMoayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir: Debugging sequential circuits using Boolean satisfiability. ICCAD 2004: 204-209
150EERolf Drechsler: Towards Formal Verification on the System Level. IEEE International Workshop on Rapid System Prototyping 2004: 2-5
149EEDragan Jankovic, Radomir S. Stankovic, Rolf Drechsler: Reduction of Sizes of Multi-Valued Decision Diagrams by Copy Propertie. ISMVL 2004: 223-228
148EEGörschwin Fey, Rolf Drechsler, Maciej J. Ciesielski: Algorithms for Taylor Expansion Diagrams. ISMVL 2004: 235-240
147EEDaniel Große, Rolf Drechsler: Checkers for SystemC designs. MEMOCODE 2004: 171-178
146EEMoayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Freescale Semiconductor, Rolf Drechsler, Alexander Smith: Debugging Sequential Circuits Using Boolean Satisfiability. MTV 2004: 44-49
145EERolf Drechsler, Junhao Shi, Görschwin Fey: Synthesis of fully testable circuits from BDDs. IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 440-443 (2004)
2003
144EERolf Drechsler, Junhao Shi, Görschwin Fey: MuTaTe: an efficient design for testability technique for multiplexor based circuits. ACM Great Lakes Symposium on VLSI 2003: 80-83
143 Rolf Drechsler, Nicole Drechsler: Minimization of Transitions by Complementation and Resequencing using Evolutionary Algorithms. Applied Informatics 2003: 109-114
142EEJunhao Shi, Görschwin Fey, Rolf Drechsler: BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability. Asian Test Symposium 2003: 290-293
141EERüdiger Ebendt, Wolfgang Günther, Rolf Drechsler: Combination of Lower Bounds in Exact BDD Minimization. DATE 2003: 10758-10763
140EEMario Hilgemeier, Nicole Drechsler, Rolf Drechsler: Fast Heuristics for the Edge Coloring of Large Graphs. DSD 2003: 230-239
139EERolf Drechsler, Nicole Drechsler: GAME-HDL: Implementation of Evolutionary Algorithms Using Hardware Description Languages. EvoWorkshops 2003: 378-387
138EEDaniel Große, Rolf Drechsler, Lothar Linhard, Gerhard Angst: Efficient Automatic Visualization of SystemC Designs. FDL 2003: 646-658
137EERolf Drechsler: Synthesizing checkers for on-line verification of System-on-Chip designs. ISCAS (4) 2003: 748-751
136EEDaniel Große, Rolf Drechsler: Formal verification of LTL formulas for SystemC designs. ISCAS (5) 2003: 245-248
135EEDenis V. Popel, Rolf Drechsler: Efficient Minimization of Multiple-valued Decision Diagrams for Incompletely Specified Functions. ISMVL 2003: 241-246
134EEDaniel Große, Görschwin Fey, Rolf Drechsler: Modeling Multi-Valued Circuits in SystemC. ISMVL 2003: 281-286
133EEGörschwin Fey, Sebastian Kinder, Rolf Drechsler: Using Games for Benchmarking and Representing the Complete Solution Space using Symbolic Techniques. ISMVL 2003: 361-366
132EED. Michael Miller, Rolf Drechsler: Augmented Sifting of Multiple-Valued Decision Diagrams. ISMVL 2003: 375-382
131EEGörschwin Fey, Rolf Drechsler: Finding Good Counter-Examples to Aid Design Verification. MEMOCODE 2003: 51-
130 Valentina Ciriani, Anna Bernasconi, Rolf Drechsler: Testability of SPP Three-Level Logic Networks. VLSI-SOC 2003: 331-336
129 Nicole Drechsler, Rolf Drechsler: Exploration of Sequential Depth by Evolutionary Algorithms. VLSI-SOC 2003: 81-85
128 Martin Keim, Rolf Drechsler, Bernd Becker, Michael Martin, Paul Molitor: Polynomial Formal Verification of Multipliers. Formal Methods in System Design 22(1): 39-58 (2003)
127EEFrank Schmiedle, Rolf Drechsler, Bernd Becker: Exact Routing with Search Space Reduction. IEEE Trans. Computers 52(6): 815-825 (2003)
126EEWolfgang Günther, Rolf Drechsler: Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams. IEEE Trans. Computers 52(9): 1196-1209 (2003)
125EERüdiger Ebendt, Wolfgang Günther, Rolf Drechsler: An improved branch and bound algorithm for exact BDD minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 22(12): 1657-1663 (2003)
124EERolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst: Recursive bi-partitioning of netlists for large number of partitions. Journal of Systems Architecture 49(12-15): 521-528 (2003)
123 Daniel Große, Rolf Drechsler: Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC. it - Information Technology 45(4): 219-226 (2003)
2002
122EEWhitney J. Townsend, Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller: Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations. ACM Great Lakes Symposium on VLSI 2002: 178-183
121EEDragan Jankovic, Radomir S. Stankovic, Rolf Drechsler: Decision Diagram Optimization Using Copy Properties. DSD 2002: 236-243
120EERolf Drechsler, Daniel Große: Reachability Analysis for Formal Verification of SystemC. DSD 2002: 337-340
119EERolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst: Recursive Bi-Partitioning of Netlists for Large Number of Partitions. DSD 2002: 38-44
118EEThomas Eschbach, Wolfgang Günther, Rolf Drechsler, Bernd Becker: Crossing Reduction by Windows Optimization. Graph Drawing 2002: 285-294
117EEMikael Kerttu, Per Lindgren, Mitchell A. Thornton, Rolf Drechsler: Switching activity estimation of finite state machines for low power synthesis. ISCAS (4) 2002: 65-68
116EED. Michael Miller, Rolf Drechsler: On the Construction of Multiple-Valued Decision Diagrams. ISMVL 2002: 245-253
115EERolf Drechsler: Evaluation of Static Variable Ordering Heuristics for MDD Construction. ISMVL 2002: 254-260
114EESherief Reda, Rolf Drechsler, Alex Orailoglu: On the Relation between SAT and BDDs for Equivalence Checking. ISQED 2002: 394-399
113EEMitchell A. Thornton, Rolf Drechsler, D. Michael Miller: Multi-Output Timed Shannon Circuits. ISVLSI 2002: 47-52
112 Mikael Kerttu, Per Lindgren, Rolf Drechsler, Mitchell A. Thornton: Low Power Optimization Techniques for BDD Mapped Finite State Machines. IWLS 2002: 143-148
111EERaik Brinkmann, Rolf Drechsler: RTL-Datapath Verification using Integer Linear Programming. VLSI Design 2002: 741-746
110 Frank Schmiedle, Nicole Drechsler, Daniel Große, Rolf Drechsler: Heuristic Learning Based on Genetic Programming. Genetic Programming and Evolvable Machines 3(4): 363-388 (2002)
109EEWolfgang Günther, Rolf Drechsler: Minimization of free BDDs. Integration 32(1-2): 41-59 (2002)
108EERolf Drechsler: Verifying integrity of decision diagrams. Integration 32(1-2): 61-75 (2002)
107EERolf Drechsler, Wolfgang Günther, Stefan Höreth: Minimization of Word-Level Decision Diagrams. Integration 33(1-2): 39-70 (2002)
2001
106EEPer Lindgren, Mikael Kerttu, Mitchell A. Thornton, Rolf Drechsler: Low power optimization technique for BDD mapped circuits. ASP-DAC 2001: 615-621
105EEMitchell A. Thornton, Rolf Drechsler: Spectral decision diagrams using graph transformations. DATE 2001: 713-719
104EERolf Drechsler, Wolfgang Günther, Lothar Linhard, Gerhard Angst: Level Assignment for Displaying Combinational Logic. DSD 2001: 148-151
103EEBernd Becker, Thomas Eschbach, Rolf Drechsler, Wolfgang Günther: Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement. DSD 2001: 54-61
102EEMigyoung Jung, Gueesang Lee, Sungju Park, Rolf Drechsler: Minimization of OPKFDDs Using Genetic Algorithms. DSD 2001: 72-78
101EENicole Drechsler, Rolf Drechsler, Bernd Becker: Multi-objective Optimisation Based on Relation Favour. EMO 2001: 154-166
100EENicole Drechsler, Frank Schmiedle, Daniel Große, Rolf Drechsler: Heuristic Learning Based on Genetic Programming. EuroGP 2001: 1-10
99EEFrank Schmiedle, Daniel Große, Rolf Drechsler, Bernd Becker: Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics. Fuzzy Days 2001: 479-491
98 Frank Schmiedle, Wolfgang Günther, Rolf Drechsler: Selection of Efficient Re-Ordering Heuristics for MDD Construction. ISMVL 2001: 299-304
97EEWolfgang Günther, Rolf Drechsler: Implementation of Read- k-times BDDs on Top of Standard BDD Packages. VLSI Design 2001: 173-178
96EEWolfgang Günther, Rolf Drechsler: Performance Driven Optimization for MUX based FPGAs. VLSI Design 2001: 311-316
95 Peer Johannsen, Rolf Drechsler: Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal Widths. VLSI-SOC 2001: 361-374
94EEDragan Jankovic, Radomir S. Stankovic, Rolf Drechsler: Decision Diagram Method for Calculation of Pruned Walsh Transform. IEEE Trans. Computers 50(2): 147-157 (2001)
93EERolf Drechsler, Wolfgang Günther, Fabio Somenzi: Using lower bounds during dynamic BDD minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 51-57 (2001)
92EERolf Drechsler, Wolfgang Günther: History-based dynamic BDD minimization. Integration 31(1): 51-63 (2001)
91EEMartin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker: Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits. J. Electronic Testing 17(1): 37-51 (2001)
90EERolf Drechsler, Detlef Sieling: Binary decision diagrams in theory and practice. STTT 3(2): 112-136 (2001)
2000
89EEWolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker: Verification of Designs Containing Black Boxes. EUROMICRO 2000: 1100-1105
88EEWolfgang Günther, Rolf Drechsler: ACTion: Combining Logic Synthesis and Technology Mapping for MUX Based FPGAs. EUROMICRO 2000: 1130-1137
87EERolf Drechsler, Wolfgang Günther, Bernd Becker: Testability of Circuits Derived from Lattice Diagrams. EUROMICRO 2000: 1188-1192
86EERolf Drechsler, Nicole Drechsler, Elke Mackensen, Tobias Schubert, Bernd Becker: Design Reuse by Modularity: A Scalable Dynamical (Re)Configurable Multiprocessor System. EUROMICRO 2000: 1425-
85 Wolfgang Günther, Rolf Drechsler: Improving EAs for Sequencing Problems. GECCO 2000: 175-180
84 Tobias Schubert, Elke Mackensen, Nicole Drechsler, Rolf Drechsler, Bernd Becker: Specialized Hardware for Implementation of Evolutionary Algorithms. GECCO 2000: 369
83 Rolf Drechsler, Wolfgang Günther: Evolutionary Synthesis of Multiplexor Circuits under Hardware Constraints. GECCO 2000: 513-518
82EEWolfgang Günther, Rolf Drechsler, Stefan Höreth: Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation. ICCD 2000: 383-388
81EEPer Lindgren, Rolf Drechsler, Bernd Becker: Minimization of Ordered Pseudo Kronecker Decision Diagrams. ICCD 2000: 504-
80EEDragan Jankovic, Wolfgang Günther, Rolf Drechsler: Lower Bound Sifting for MDDs. ISMVL 2000: 193-198
79EEFrank Schmiedle, Wolfgang Günther, Rolf Drechsler: Dynamic Re-Encoding During MDD Minimization. ISMVL 2000: 239-244
78EERolf Drechsler, Mitchell A. Thornton, David Wessels: MDD-Based Synthesis of Multi-Valued Logic Networks. ISMVL 2000: 41-46
77EEMitchell A. Thornton, Rolf Drechsler, Wolfgang Günther: A Method for Approximate Equivalence Checking. ISMVL 2000: 447-452
76EERolf Drechsler, Mitchell A. Thornton: Computation of Spectral Information from Logic Netlists. ISMVL 2000: 53-58
75EERolf Drechsler, Nicole Drechsler, Wolfgang Günther: Fast exact minimization of BDD's. IEEE Trans. on CAD of Integrated Circuits and Systems 19(3): 384-389 (2000)
74EEWolfgang Günther, Rolf Drechsler: On the computational power of linearly transformed BDDs. Inf. Process. Lett. 75(3): 119-125 (2000)
73EERolf Drechsler, Bernd Becker, Nicole Drechsler: OKFDD minimization by genetic algorithms with application to circuit design. Integration 28(2): 121-139 (2000)
72EEA. Zuzek, Rolf Drechsler, Mitchell A. Thornton: Boolean function representation and spectral characterization using AND/OR graphs. Integration 29(2): 101-116 (2000)
71EEWolfgang Günther, Rolf Drechsler: ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs. Journal of Systems Architecture 46(14): 1321-1334 (2000)
1999
70EEYibin Ye, Kaushik Roy, Rolf Drechsler: Power Consumption in XOR-Based Circuits. ASP-DAC 1999: 299-302
69EERolf Drechsler, Nicole Drechsler: Exploiting Don't Caers During Data Sequencing using Genetic Algorithms. ASP-DAC 1999: 303-
68EEWolfgang Günther, Rolf Drechsler: Minimization of Free BDDs. ASP-DAC 1999: 323-326
67EERolf Drechsler, Wolfgang Günther: Using Lower Bounds During Dynamic BDD Minimization. DAC 1999: 29-32
66EEStefan Höreth, Rolf Drechsler: Formal Verification of Word-Level Specifications. DATE 1999: 52-57
65EEMitchell A. Thornton, J. P. Williams, Rolf Drechsler, Nicole Drechsler: Variable Reordering for Shared Binary Decision Diagrams Using Output Probabilities. DATE 1999: 758-759
64EERolf Drechsler, Wolfgang Günther: Generation of Optimal Universal Logic Modules. EUROMICRO 1999: 1080-1085
63EERolf Drechsler, Dragan Jankovic, Radomir S. Stankovic: Generic Implementation of DD Packages in MVL. EUROMICRO 1999: 1352-1359
62EERolf Drechsler: Checking Integrity During Dynamic Reordering in Decision Diagrams. EUROMICRO 1999: 1360-1367
61 Nicole Drechsler, Rolf Drechsler, Bernd Becker: Multi-objected Optimization in Evolutionary Algorithms Using Satisfiability Classes. Fuzzy Days 1999: 108-117
60 Nicole Drechsler, Wolfgang Günther, Rolf Drechsler: Efficient Graph Coloring by Evolutionary Algorithms. Fuzzy Days 1999: 30-39
59EEWolfgang Günther, Rolf Drechsler: Efficient manipulation algorithms for linearly transformed BDDs. ICCAD 1999: 50-54
58EEPer Lindgren, Rolf Drechsler, Bernd Becker: Synthesis of Pseudo Kronecker Lattice Diagrams. ICCD 1999: 307-310
57EEWolfgang Günther, Rolf Drechsler: Minimization of BDDs using linear transformations based on evolutionary techniques. ISCAS (1) 1999: 387-390
56EERolf Drechsler, Marc Herbstritt, Bernd Becker: Grouping heuristics for word-level decision diagrams. ISCAS (1) 1999: 411-414
55EEFrank Schmiedle, Rolf Drechsler, Bernd Becker: Exact channel routing using symbolic representation. ISCAS (6) 1999: 394-397
54EEFranc Brglez, Rolf Drechsler: Design of experiments in CAD: context and new data sets for ISCAS'99. ISCAS (6) 1999: 424-427
53EEWolfgang Günther, Rolf Drechsler: Creating hard problem instances in logic synthesis using exact minimization. ISCAS (6) 1999: 436-439
52 Rolf Drechsler, Wolfgang Günther: History-Based Dynamic Minimization During BDD Construction. VLSI 1999: 334-345
51 Rolf Drechsler: Preudo-Kronecker Expressions for Symmetric Functions. IEEE Trans. Computers 48(9): 987-990 (1999)
50 Rolf Drechsler: Evolutionary Algorithms for VLSI CAD [book Review]. IEEE Trans. Evolutionary Computation 3(3): 251-253 (1999)
49EEChristoph Scholl, Dirk Möller, Paul Molitor, Rolf Drechsler: BDD minimization using symmetries. IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 81-100 (1999)
48EERolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker: Testability of 2-Level AND/EXOR Circuits. J. Electronic Testing 14(3): 219-225 (1999)
1998
47 Rolf Drechsler, Stefan Höreth: Manipulation of *BMDs. ASP-DAC 1998: 433-438
46 Gueesang Lee, Rolf Drechsler: ETDD-Based Synthesis of Term-Based FPGAs for Incompletely Specified Boolean Functions. ASP-DAC 1998: 75-80
45EERolf Drechsler, Nicole Drechsler, Wolfgang Günther: Fast Exact Minimization of BDDs. DAC 1998: 200-205
44EEStefan Höreth, Rolf Drechsler: Dynamic Minimization of Word-Level Decision Diagrams. DATE 1998: 612-617
43EEWolfgang Günther, Rolf Drechsler: Linear Transformations and Exact Minimization of BDDs. Great Lakes Symposium on VLSI 1998: 325-330
42EEMartin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker: Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm. ISMVL 1998: 215-
41EED. Miller, Rolf Drechsler: Implementing a Multiple-Valued Decision Diagram Package. ISMVL 1998: 52-57
40EEPer Lindgren, Rolf Drechsler, Bernd Becker: Look-up Table FPGA Synthesis from Minimized Multi-Valued Pseudo Kronecker Expressions. ISMVL 1998: 95-
39EERolf Drechsler: Verifying Integrity of Decision Diagrams. SAFECOMP 1998: 380-389
38 Rolf Drechsler, Bernd Becker, Andrea Jahnke: On Variable Ordering and Decomposition Type Choice in OKFDDs. IEEE Trans. Computers 47(12): 1398-1403 (1998)
37EERolf Drechsler, Bernd Becker: Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions. IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 965-973 (1998)
36EERolf Drechsler, Martin Sauerhoff, Detlef Sieling: The complexity of the inclusion operation on OFDD's. IEEE Trans. on CAD of Integrated Circuits and Systems 17(5): 457-459 (1998)
1997
35EEAndreas Hett, Rolf Drechsler, Bernd Becker: Fast and efficient construction of BDDs by reordering based synthesis. ED&TC 1997: 168-175
34EERolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker: Testability of 2-level AND/EXOR circuits. ED&TC 1997: 548-553
33EEChristoph Scholl, Rolf Drechsler, Bernd Becker: Functional simulation using binary decision diagrams. ICCAD 1997: 8-12
32EERolf Drechsler, Martin Keim, Bernd Becker: Fault Simulation in Sequential Multi-Valued Logic Networks. ISMVL 1997: 145-
31EECraig M. Files, Rolf Drechsler, Marek A. Perkowski: Functional Decomposition of MVL Functions Using Multi-Valued Decision Diagrams. ISMVL 1997: 27-
30EERadomir S. Stankovic, Rolf Drechsler: Circuit Design from Kronecker Galois Field Decision Diagrams for Multiple-Valued Functions. ISMVL 1997: 275-280
29EERolf Drechsler, Martin Keim, Bernd Becker: Sympathy-MV: Fast Exact Minimization of Fixed Polarity Multi-Valued Linear Expressions. ISMVL 1997: 66-
28 Rolf Drechsler, Bernd Becker, Stefan Ruppertz: Manipulation Algorithms for K*BMDs. TACAS 1997: 4-18
27EEBernd Becker, Rolf Drechsler, Sudhakar M. Reddy: (Quasi-) Linear Path Delay Fault Tests for Adders. VLSI Design 1997: 101-105
26EEBernd Becker, Rolf Drechsler: Decision Diagrams in Synthesis - Algorithms, Applications and Extensions. VLSI Design 1997: 46-50
25EERolf Drechsler: Pseudo Kronecker Expressions for Symmetric Functions. VLSI Design 1997: 511-513
24EEMartin Keim, Michael Martin, Bernd Becker, Rolf Drechsler, Paul Molitor: Polynomial Formal Verification of Multipliers. VTS 1997: 150-157
23 Bernd Becker, Rolf Drechsler, Michael Theobald: On the Expressive Power of OKFDDs. Formal Methods in System Design 11(1): 5-21 (1997)
22EERolf Drechsler, Bernd Becker, Stefan Ruppertz: The K*BMD: A Verification Data Structure. IEEE Design & Test of Computers 14(2): 51-59 (1997)
21EERolf Drechsler, Bernd Becker: Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 1-5 (1997)
1996
20EEHarry Hengster, Rolf Drechsler, Bernd Becker, Stefan Eckrich, Tonja Pfeiffer: AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth. Asian Test Symposium 1996: 148-
19EERolf Drechsler: Verification of Multi-Valued Logic Networks. ISMVL 1996: 10-15
18EERolf Drechsler, Nicole Göckel, Bernd Becker: Learning Heuristics for OBDD Minimization by Evolutionary Algorithms. PPSN 1996: 730-739
17 Rolf Drechsler, Michael Theobald, Bernd Becker: Fast OFFD-Based Minimization of Fixed Polarity Reed-Muller Expressions. IEEE Trans. Computers 45(11): 1294-1299 (1996)
1995
16EERolf Drechsler, Bernd Becker: Learning heuristics by genetic algorithms. ASP-DAC 1995
15EEBernd Becker, Rolf Drechsler, Michael Theobald: OKFDDs versus OBDDs and OFDDs. ICALP 1995: 475-486
14EERolf Drechsler, Bernd Becker: Dynamic minimization of OKFDDs. ICCD 1995: 602-
13EERolf Drechsler, Rolf Krieger, Bernd Becker: Random Pattern Fault Simulation in Multi-Valued Circuits. ISMVL 1995: 98-103
12 Bernd Becker, Rolf Drechsler, Ralph Werchner: On the Relation Betwen BDDs and FDDs. LATIN 1995: 72-83
11EEHarry Hengster, Rolf Drechsler, Bernd Becker: On the application of local circuit transformations with special emphasis on path delay fault testability. VTS 1995: 387-392
10EEBernd Becker, Rolf Drechsler, Paul Molitor: On the generation of area-time optimal testable adders. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1049-1066 (1995)
9 Bernd Becker, Rolf Drechsler, Ralph Werchner: On the Relation between BDDs and FDDs. Inf. Comput. 123(2): 185-197 (1995)
8EEHarry Hengster, Rolf Drechsler, Bernd Becker: On local transformations and path delay fault testability. J. Electronic Testing 7(3): 173-191 (1995)
1994
7EERolf Drechsler, Andisheh Sarabi, Michael Theobald, Bernd Becker, Marek A. Perkowski: Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams. DAC 1994: 415-419
6 Bernd Becker, Rolf Drechsler: Testability of Circuits Derived from Functional Decision Diagrams. EDAC-ETC-EUROASIC 1994: 667
5EERolf Drechsler, Bernd Becker, Michael Theobald: Fast OFDD based minimization of fixed polarity Reed-Muller expressions. EURO-DAC 1994: 2-7
4EERolf Drechsler: BiTeS: a BDD based test pattern generator for strong robust path delay faults. EURO-DAC 1994: 322-327
3 Bernd Becker, Rolf Drechsler: OFDD Based Minimization of Fixed Polarity Reed-Muller Expressions Using Hybrid Genetic Algorithms. ICCD 1994: 106-110
2 Bernd Becker, Rolf Drechsler: Efficient Graph Based Representation of Multi-Valued Functions with an Application to Genetic Algorithms. ISMVL 1994: 65-72
1 Harry Hengster, Rolf Drechsler, Bernd Becker: Testability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault Model. VLSI Design 1994: 123-126

Coauthor Index

1Magdy S. Abadir [146] [151] [161] [168]
2Moayad Fahim Ali [146] [151] [161] [168]
3Mahsan Amoui [202]
4Gerhard Angst [104] [119] [124] [138] [204] [231]
5Walter Anheier [224]
6Jens Bargfrede [224]
7Bernd Becker [1] [2] [3] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [20] [21] [22] [23] [24] [26] [27] [28] [29] [32] [33] [34] [35] [37] [38] [40] [42] [48] [55] [56] [58] [61] [73] [81] [84] [86] [87] [89] [91] [99] [101] [103] [118] [127] [128]
8Anna Bernasconi [130] [176] [189] [209] [217] [220]
9Roderick Bloem [186] [221] [236]
10Anthony Brabazon [215] [237]
11Jürgen Branke [158] [174] [193]
12Cécile Braunstein [243]
13Andreas Breiter [206]
14Franc Brglez [54]
15Raik Brinkmann [111]
16Stefano Cagnoni [158] [174] [193] [215] [237]
17Gianni Di Caro [215] [237]
18Xiaobo Chen [213]
19Maciej J. Ciesielski [148]
20Valentina Ciriani [130] [176] [189] [209] [217] [220]
21David W. Corne (David Corne) [158] [174]
22Ernesto Costa (Ernesto Jorge Costa) [193]
23Carlos Cotta [193]
24Nicole Drechsler [42] [45] [60] [61] [65] [69] [73] [75] [84] [86] [89] [91] [100] [101] [110] [129] [139] [140] [143] [152] [188]
25Gerhard W. Dueck [213] [227] [228] [240] [244]
26Rüdiger Ebendt [125] [141] [155] [156] [159] [160] [163] [171] [175] [181] [184] [214] [238]
27Stefan Eckrich [20]
28Stephan Eggersglüß [196] [199] [201] [205] [218] [225]
29Anikó Ekárt [237]
30Thomas Eschbach [103] [118] [119] [124]
31Anna Esparcia-Alcázar [237]
32A. Sima Etaner-Uyar (Sima Uyar) [215] [237]
33Muddassar Farooq [215] [237]
34Görschwin Fey [131] [133] [134] [142] [144] [145] [148] [152] [153] [157] [164] [165] [167] [172] [173] [177] [179] [180] [183] [186] [190] [191] [196] [198] [199] [201] [205] [209] [211] [217] [218] [221] [223] [231] [233] [236] [243] [247]
35Craig M. Files [31]
36Andreas Fink [215] [237]
37Stefan Frehse [244]
38Christian Genz [167] [182] [197] [204] [208] [242]
39Mario Giacobini [215] [237]
40Manfred Glesner [229]
41Sabine Glesner [195]
42Andreas Glowatz [164] [199] [201] [218]
43Nicole Göckel [18]
44Daniel Große [99] [100] [110] [120] [123] [134] [136] [138] [147] [162] [166] [167] [169] [170] [190] [192] [196] [200] [202] [207] [212] [213] [214] [219] [222] [227] [228] [230] [240] [244] [245] [248]
45Wolfgang Günther [43] [45] [52] [53] [57] [59] [60] [64] [67] [68] [71] [74] [75] [77] [79] [80] [82] [83] [85] [87] [88] [89] [92] [93] [96] [97] [98] [103] [104] [107] [109] [118] [119] [124] [125] [126] [141] [155] [156] [159]
46Friedrich Hapke [164] [199] [201] [218]
47Joachim Hartmann [34] [48]
48Harry Hengster [1] [8] [11] [20] [34] [48]
49Marc Herbstritt [56]
50Andreas Hett [35]
51Mario Hilgemeier [140] [152]
52Stefan Höreth [44] [47] [66] [82] [107]
53Andrea Jahnke [38]
54Dragan Jankovic [63] [80] [94] [121] [149]
55Yaochu Jin [158] [174]
56Peer Johannsen [95]
57Colin G. Johnson [158]
58Migyoung Jung [102]
59Tommi A. Junttila [239]
60Martin Keim [24] [29] [32] [42] [91] [128]
61Mikael Kerttu [106] [112] [117]
62Sebastian Kinder [133] [165] [179] [210] [216]
63Wolfgang Klingauf [207]
64Thomas Klotz [233]
65Jens Knoop [195]
66Klaus Koch [224]
67Rolf Krieger [13]
68Ulrich Kühne [162] [169] [192] [200] [212] [219] [243] [245] [248]
69Gueesang Lee [46] [102]
70Joanne Lee [154]
71Per Lindgren [40] [58] [81] [106] [112] [117]
72Lothar Linhard [104] [119] [124] [138] [204] [231]
73Doina Logofatu [187] [226]
74Evelyne Lutton [193] [215]
75Penousal Machado [158] [174] [193] [215]
76Elke Mackensen [84] [86]
77Elena Marchiori [158] [174]
78Michael Martin [24] [128]
79Jon McCormack [237]
80Marc Messing [231]
81D. Miller [41]
82D. Michael Miller [113] [116] [122] [132]
83Stefan Minner [215]
84Paul Molitor [10] [24] [49] [128]
85Dirk Möller [49]
86Jason H. Moore [193]
87Beate Muranko [178] [194]
88Tudor Murgan [229]
89Ilkka Niemelä [239]
90Michael O'Neill [215] [237]
91Alex Orailoglu [114]
92Murthy Palla [224]
93Sujan Pandey [197] [229] [234] [235]
94Sungju Park [102]
95Hernan Peraza [207]
96Marek A. Perkowski [7] [31]
97Tonja Pfeiffer [20]
98Denis V. Popel [135]
99Günther R. Raidl [158]
100Sherief Reda [114]
101Sudhakar M. Reddy [27]
102Frank Rogin [208] [233]
103Juan Romero [174] [193] [215] [237]
104Franz Rothlauf [158] [174] [193] [215] [237]
105Kaushik Roy [70]
106Steffen Rülke [208] [233]
107Stefan Ruppertz [22] [28]
108Sean Safarpour [146] [151] [154] [161] [168] [173] [185] [191]
109Andisheh Sarabi [7]
110Martin Sauerhoff [36]
111Horst Schäfer [34] [48]
112Jürgen Schlöffel [164] [199] [201] [218]
113Frank Schmiedle [55] [79] [98] [99] [100] [110] [127]
114Christoph Scholl [33] [49]
115Tobias Schubert [84] [86]
116Freescale Semiconductor [146]
117Junhao Shi [142] [144] [145] [153] [164] [172] [183]
118Robert Siegmund [230]
119Detlef Sieling [36] [90]
120Alexander Smith [146] [151]
121George D. Smith [158] [174] [193]
122Mathias Soeken [222]
123Fabio Somenzi [93]
124Giovanni Squillero [158] [174] [193] [215] [237]
125Stefan Staber [186] [221]
126Radomir S. Stankovic [30] [63] [94] [121] [149]
127André Sülflow [188] [203] [236] [243] [247]
128Hideyuki Takagi [193] [215]
129Lisa Teuber [227]
130Michael Theobald [5] [7] [15] [17] [23]
131Mitchell A. Thornton (Mitchell Aaron Thornton) [65] [72] [76] [77] [78] [105] [106] [112] [113] [117] [122] [202]
132Daniel Tille [201] [211] [218] [232] [241]
133Whitney J. Townsend [122]
134Andreas G. Veneris [146] [151] [154] [161] [168] [173] [185] [191]
135Tiziano Villa [189] [220]
136Tim Warode [198]
137Ralph Werchner [9] [12]
138David Wessels [78]
139Robert Wille [196] [222] [227] [228] [230] [231] [240] [244] [246] [248]
140J. P. Williams [65]
141Shengxiang Yang [215] [237]
142Yibin Ye [70]
143A. Zuzek [72]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)