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Mindaugas Drazdziulis Vis

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*2007
6EEMinh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis: High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process. DSD 2007: 249-256
5EEMinh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson: Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays. ISQED 2007: 185-191
4EEMindaugas Drazdziulis, Per Larsson-Edefors, Lars J. Svensson: Overdrive Power-Gating Techniques for Total Power Minimization. ISVLSI 2007: 125-132
2006
3EEMinh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson: Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration. ISQED 2006: 557-563
2005
2EEMagnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors, Henrik Eriksson: A low-leakage twin-precision multiplier using reconfigurable power gating. ISCAS (2) 2005: 1654-1657
2004
1 Mindaugas Drazdziulis, Per Larsson-Edefors: Evaluation of power cut-off techniques in the presence of gate leakage. ISCAS (2) 2004: 745-748

Coauthor Index

1Lars Bengtsson [3] [5]
2Minh Quang Do [3] [5] [6]
3Henrik Eriksson [2]
4Per Larsson-Edefors [1] [2] [3] [4] [5] [6]
5Magnus Själander [2]
6Lars J. Svensson [4]

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)