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Yong Dou Vis

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*2009
33EEYong Dou, Ralf Gruber, Josef M. Joller: Advanced Parallel Processing Technologies, 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009, Proceedings Springer 2009
32EEJie Zhou, Yong Dou, Jianxun Zhao, Fei Xia, Yuanwu Lei, Yuxing Tang: A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA. APPT 2009: 110-122
31EEJinbo Xu, Yong Dou, YuXing Tang, Xiaodong Wang: Implementation of Rotation Invariant Multi-View Face Detection on FPGA. APPT 2009: 82-94
30EEYong Dou, Fei Xia, Jingfei Jiang: Fine-grained parallel application specific computing for RNA secondary structure prediction using SCFGS on FPGA. CASES 2009: 107-116
29 Guangming Liu, Fei Xia, Yong Dou, Xin Liu: FPGA-based Memory-efficient Parallel RNA Secondary Structure Prediction Accelerator Using SCFGs. PDPTA 2009: 814-820
28EEFei Xia, Yong Dou, Xingming Zhou, Xuejun Yang, Jiaqing Xu, Yang Zhang: Fine-grained parallel RNAalifold algorithm for RNA secondary structure prediction on FPGA. BMC Bioinformatics 10(S-1): (2009)
27EEDawei Wang, Sikun Li, Yong Dou: Loop Kernel Pipelining Mapping onto Coarse-Grained Reconfigurable Architecture for Data-Intensive Applications. JSW 4(1): 81-89 (2009)
26EEYong Dou, Guiming Wu, Jinhui Xu, Xingming Zhou: A coarse-grained reconfigurable computing architecture with loop self-pipelining. Science in China Series F: Information Sciences 52(4): 575-587 (2009)
2008
25EEJie Zhou, Yong Dou, Yuanwu Lei, Yazhuo Dong: Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. ARC 2008: 254-259
24EEFei Xia, Yong Dou, Jinbo Xu: Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension. ARC 2008: 39-50
23EEDawei Wang, Sikun Li, Yong Dou: Collaborative hardware/software partition of coarse-grained reconfigurable system using evolutionary ant colony optimization. ASP-DAC 2008: 679-684
22 Fei Xia, Yong Dou, Jiaqing Xu: Fine-Grained Parallel Zuker Algorithm Accelerator with Storage Optimization on FPGA. BIOCOMP 2008: 538-544
21EEFei Xia, Yong Dou, Jiaqing Xu: Families of FPGA-Based Accelerators for BLAST Algorithm with Multi-seeds Detection and Parallel Extension. BIRD 2008: 43-57
20EEJie Zhou, Yong Dou, Yuanwu Lei, Jinbo Xu, Yazhuo Dong: Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. HPCC 2008: 182-189
19EEYong Dou, Fei Xia, Xingming Zhou, Xuejun Yang: Fine-grained parallel application specific computing for RNA secondary structure prediction on FPGA. ICCD 2008: 240-247
18EEYong Dou, Lin Deng, Jinhui Xu, Yi Zheng: DMA Performance Analysis and Multi-core Memory Optimization for SWIM Benchmark on the Cell Processor. ISPA 2008: 170-179
17EEJinbo Xu, Yong Dou, Jie Zhou: Rectangularly Multi-Module Memory System with Table-Based Dynamic Addressing Scheme. NAS 2008: 334-341
2007
16EEFei Xia, Yong Dou: Reducing Storage Requirements in Accelerating Algorithm of Global BioSequence Alignment on FPGA. APPT 2007: 90-99
15EEYazhuo Dong, Yong Dou, Jie Zhou: Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware. ARC 2007: 110-121
14EEYong Dou, Jinhui Xu, Guiming Wu: The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining. ARC 2007: 155-166
13EEXiaodong Yang, Shengmei Mou, Yong Dou: FPGA-Accelerated Molecular Dynamics Simulations: An Overview. ARC 2007: 293-301
12EEYong Dou, Jie Zhou, Yuanwu Lei, Xingming Zhou: FPGA SAR Processor with Window Memory Accesses. ASAP 2007: 95-100
11EEYazhuo Dong, Yong Dou: A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications. ASP-DAC 2007: 523-528
10EEYong Dou, Jinbo Xu: FPGA-Accelerated Active Shape Model for Real-Time People Tracking. Asia-Pacific Computer Systems Architecture Conference 2007: 268-279
9EESikun Li, Dawei Wang, Tun Li, Yong Dou: Distributed Collaborative Partition Method of Reconfigurable SoC Using Ant Colony Optimization. CSCWD 2007: 133-138
8EEJinbo Xu, Yong Dou, Junfeng Li, Xingming Zhou, Qiang Dou: FPGA Accelerating Algorithms of Active Shape Model in People Tracking Applications. DSD 2007: 432-435
7EEBao-Feng Li, Yong Dou: FIDP: A Novel Architecture for Lifting-Based 2D DWT in JPEG2000. MMM (2) 2007: 373-382
2006
6EEJinhui Xu, Guiming Wu, Yong Dou, Yazhuo Dong: Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining. Asia-Pacific Computer Systems Architecture Conference 2006: 567-573
5EESong Lu, BaoHua Fan, Yong Dou, Xiaodong Yang: Clustering Multicast on Hypercube Network. HPCC 2006: 61-70
4EEXue-Jun Yang, Yong Dou, Qing-Feng Hu: Progress and Challenges in High Performance Computer Technology. J. Comput. Sci. Technol. 21(5): 674-681 (2006)
2005
3EEYuXing Tang, Kun Deng, Xiaodong Wang, Yong Dou, Xingming Zhou: RIMP: Runtime Implicit Predication. APPT 2005: 71-80
2EEYong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, Georgi Gaydadjiev: 64-bit floating-point FPGA matrix multiplication. FPGA 2005: 86-95
2003
1EEYong Dou, Xicheng Lu: LEAP: A Data Driven Loop Engine on Array Processor. APPT 2003: 12-22

Coauthor Index

1Kun Deng [3]
2Lin Deng [18]
3Yazhuo Dong [6] [11] [15] [20] [25]
4Qiang Dou [8]
5BaoHua Fan [5]
6Georgi Gaydadjiev (Georgi Nedeltchev Gaydadjiev) [2]
7Ralf Gruber [33]
8Qing-Feng Hu [4]
9Jingfei Jiang [30]
10Josef M. Joller [33]
11Georgi Kuzmanov [2]
12Yuanwu Lei [12] [20] [25] [32]
13Bao-Feng Li [7]
14Junfeng Li [8]
15Sikun Li [9] [23] [27]
16Tun Li [9]
17Guangming Liu [29]
18Xin Liu [29]
19Song Lu [5]
20Xicheng Lu [1]
21Shengmei Mou [13]
22YuXing Tang [3] [31]
23Yuxing Tang [32]
24Stamatis Vassiliadis [2]
25Dawei Wang [9] [23] [27]
26Xiaodong Wang [3] [31]
27Guiming Wu [6] [14] [26]
28Fei Xia [16] [19] [21] [22] [24] [28] [29] [30] [32]
29Jiaqing Xu [21] [22] [28]
30Jinbo Xu [8] [10] [17] [20] [24] [31]
31Jinhui Xu [6] [14] [18] [26]
32Xiaodong Yang [5] [13]
33Xue-Jun Yang [4]
34Xuejun Yang [19] [28]
35Yang Zhang [28]
36Jianxun Zhao [32]
37Yi Zheng [18]
38Jie Zhou [12] [15] [17] [20] [25] [32]
39Xingming Zhou [3] [8] [12] [19] [26] [28]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)