| 2007 |
|---|
| 125 | EE | Saumya Chandra,
Kanishka Lahiri,
Anand Raghunathan,
Sujit Dey:
System-on-Chip Power Management Considering Leakage Power Variations.
DAC 2007: 877-882 |
| 124 | EE | Naomi Ramos,
Debashis Panigrahi,
Sujit Dey:
Dynamic adaptation policies to improve quality of service of real-time multimedia applications in IEEE 802.11e WLAN Networks.
Wireless Networks 13(4): 511-535 (2007) |
| 2006 |
|---|
| 123 | EE | Krishna Sekar,
Kanishka Lahiri,
Anand Raghunathan,
Sujit Dey:
Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms.
DATE 2006: 728-733 |
| 122 | EE | Saumya Chandra,
Kanishka Lahiri,
Anand Raghunathan,
Sujit Dey:
Considering process variations during system-level power analysis.
ISLPED 2006: 342-345 |
| 121 | EE | Chong Zhao,
Sujit Dey:
Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO).
ISQED 2006: 133-140 |
| 2005 |
|---|
| 120 | EE | Chong Zhao,
Yi Zhao,
Sujit Dey:
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits.
DAC 2005: 190-195 |
| 119 | EE | Krishna Sekar,
Kanishka Lahiri,
Anand Raghunathan,
Sujit Dey:
FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology.
DAC 2005: 571-574 |
| 118 | EE | Saumya Chandra,
Sujit Dey:
Addressing Computational and Networking Constraints to Enable Video Streaming from Wireless Appliances.
ESTImedia 2005: 27-32 |
| 117 | EE | Chong Zhao,
Sujit Dey,
Xiaoliang Bai:
Soft-Spot Analysis: Targeting Compound Noise Effects in Nanometer Circuits.
IEEE Design & Test of Computers 22(4): 362-375 (2005) |
| 116 | EE | Naomi Ramos,
Debashis Panigrahi,
Sujit Dey:
Quality of service provisioning in 802.11e networks: challenges, approaches, and future directions.
IEEE Network 19(4): 14-20 (2005) |
| 2004 |
|---|
| 115 | EE | Chong Zhao,
Xiaoliang Bai,
Sujit Dey:
A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits.
DAC 2004: 894-899 |
| 114 | EE | Krishna Sekar,
Kanishka Lahiri,
Sujit Dey:
Configurable Platforms With Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips.
VLSI Design 2004: 307- |
| 113 | EE | Yi Zhao,
Sujit Dey,
Li Chen:
Double sampling data checking technique: an online testing solution for multisource noise-induced errors on on-chip interconnects and buses.
IEEE Trans. VLSI Syst. 12(7): 746-755 (2004) |
| 112 | EE | Ganesh Lakshminarayana,
Anand Raghunathan,
Kamal S. Khouri,
Niraj K. Jha,
Sujit Dey:
Common-case computation: a high-level energy and performance optimization technique.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 33-49 (2004) |
| 111 | EE | Jennifer L. Wong,
Miodrag Potkonjak,
Sujit Dey:
Optimizing designs using the addition of deflection operations.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 50-59 (2004) |
| 110 | EE | Kanishka Lahiri,
Anand Raghunathan,
Ganesh Lakshminarayana,
Sujit Dey:
Design of high-performance system-on-chips using communication architecture tuners.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 620-636 (2004) |
| 109 | EE | Kanishka Lahiri,
Anand Raghunathan,
Sujit Dey:
Efficient power profiling for battery-driven embedded system design.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(6): 919-932 (2004) |
| 108 | EE | Kanishka Lahiri,
Anand Raghunathan,
Sujit Dey:
Design space exploration for optimizing on-chip communication architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(6): 952-961 (2004) |
| 107 | EE | Weidong Wang,
Anand Raghunathan,
Niraj K. Jha,
Sujit Dey:
Resource budgeting for Multiprocess High-level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1010-1019 (2004) |
| 106 | EE | Xiaoliang Bai,
Rajit Chandra,
Sujit Dey,
P. V. Srinivas:
Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(8): 1256-1263 (2004) |
| 105 | EE | Xiaoliang Bai,
Sujit Dey:
High-level crosstalk defect Simulation methodology for system-on-chip interconnects.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1355-1361 (2004) |
| 2003 |
|---|
| 104 | EE | Li Chen,
Srivaths Ravi,
Anand Raghunathan,
Sujit Dey:
A scalable software-based self-test methodology for programmable processors.
DAC 2003: 548-553 |
| 103 | | Dong-Gi Lee,
Sujit Dey:
Addressing Server Latency and Capacity to Enable Fast and Affordable Wireless Image Data Services.
ESTImedia 2003: 40-47 |
| 102 | EE | Krishna Sekar,
Kanishka Lahiri,
Sujit Dey:
Dynamic Platform Management for Configurable Platform-Based System-on-Chips.
ICCAD 2003: 641-649 |
| 101 | EE | Yi Zhao,
Sujit Dey:
Separate Dual-Transistor Registers - A Circuit Solution for On-line Testing of Transient Error in UDSM-IC.
IOLTS 2003: 7-11 |
| 100 | EE | Xiaoliang Bai,
Rajit Chandra,
Sujit Dey,
P. V. Srinivas:
Noise-Aware Driver Modeling for Nanometer Technology.
ISQED 2003: 177-182 |
| 99 | EE | Xiaoliang Bai,
Sujit Dey,
Angela Krstic:
HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk.
ITC 2003: 112-121 |
| 98 | EE | Weidong Wang,
Niraj K. Jha,
Anand Raghunathan,
Sujit Dey:
High-level Synthesis of Multi-process Behavioral Descriptions.
VLSI Design 2003: 467-473 |
| 97 | EE | Anand Raghunathan,
Sujit Dey,
Niraj K. Jha:
High-level macro-modeling and estimation techniques for switching activity and power consumption.
IEEE Trans. VLSI Syst. 11(4): 538-557 (2003) |
| 96 | EE | Yi Zhao,
Sujit Dey:
Fault-coverage analysis techniques of crosstalk in chip interconnects.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 770-782 (2003) |
| 2002 |
|---|
| 95 | EE | Luciano Lavagno,
Sujit Dey,
Rajesh Gupta:
Specification, Modeling and Design Tools for System-on-Chip.
ASP-DAC 2002: 21-23 |
| 94 | EE | Kanishka Lahiri,
Sujit Dey,
Debashis Panigrahi,
Anand Raghunathan:
Battery-Driven System Design: A New Frontier in Low Power Design.
ASP-DAC 2002: 261-267 |
| 93 | EE | Debashis Panigrahi,
Clark N. Taylor,
Sujit Dey:
A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication.
ASP-DAC 2002: 553-560 |
| 92 | EE | Kanishka Lahiri,
Anand Raghunathan,
Sujit Dey:
Fast system-level power profiling for battery-efficient system design.
CODES 2002: 157-162 |
| 91 | EE | Li Chen,
Sujit Dey:
Software-based diagnosis for processors.
DAC 2002: 259-262 |
| 90 | EE | Angela Krstic,
Wei-Cheng Lai,
Kwang-Ting Cheng,
Li Chen,
Sujit Dey:
Embedded software-based self-testing for SoC design.
DAC 2002: 355-360 |
| 89 | EE | Kanishka Lahiri,
Sujit Dey,
Anand Raghunathan:
Communication architecture based power management for battery efficient system design.
DAC 2002: 691-696 |
| 88 | EE | Clark N. Taylor,
Debashis Panigrahi,
Sujit Dey:
Design of an Adaptive Architecture for Energy Efficient Wireless Image Communication.
Embedded Processor Design Challenges 2002: 260-273 |
| 87 | EE | Yi Zhao,
Li Chen,
Sujit Dey:
On-Line Testing of Multi-Source Noise-Induced Errors on the Interconnects and Buses of System-on-Chips.
ITC 2002: 491-499 |
| 86 | EE | Luciano Lavagno,
Sujit Dey,
Rajesh K. Gupta:
Specification, Modeling and Design Tools for System-on-Chip (Tutorial Abstract).
VLSI Design 2002: 21-23 |
| 85 | EE | Kanishka Lahiri,
Anand Raghunathan,
Sujit Dey,
Debashis Panigrahi:
Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design.
VLSI Design 2002: 261-267 |
| 84 | EE | Debashis Panigrahi,
Clark N. Taylor,
Sujit Dey:
A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication.
VLSI Design 2002: 553- |
| 83 | EE | C.-H. Chia,
Sujit Dey,
Faraydon Karim,
Haluk Konuk,
Keesup Kim:
Validation and Test of Network Processors and ASICs.
VTS 2002: 407-410 |
| 82 | EE | Krishna Sekar,
Sujit Dey:
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects.
VTS 2002: 417-422 |
| 81 | EE | Kanishka Lahiri,
Sujit Dey,
Anand Raghunathan:
Communication-Based Power Management.
IEEE Design & Test of Computers 19(4): 118-130 (2002) |
| 80 | EE | Angela Krstic,
Wei-Cheng Lai,
Kwang-Ting Cheng,
Li Chen,
Sujit Dey:
Embedded Software-Based Self-Test for Programmable Core-Based Designs.
IEEE Design & Test of Computers 19(4): 18-27 (2002) |
| 79 | EE | Faraydon Karim,
Anh Nguyen,
Sujit Dey:
An Interconnect Architecture for Networking Systems on Chips.
IEEE Micro 22(5): 36-45 (2002) |
| 78 | EE | Marcello Lajolo,
Anand Raghunathan,
Sujit Dey,
Luciano Lavagno:
Cosimulation-based power estimation for system-on-chip design.
IEEE Trans. VLSI Syst. 10(3): 253-266 (2002) |
| 2001 |
|---|
| 77 | EE | Li Chen,
Xiaoliang Bai,
Sujit Dey:
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores.
DAC 2001: 317-320 |
| 76 | EE | Faraydon Karim,
Anh Nguyen,
Sujit Dey,
Ramesh Rao:
On-Chip Communication Architecture for OC-768 Network Processors.
DAC 2001: 678-683 |
| 75 | EE | Clark N. Taylor,
Sujit Dey,
Yi Zhao:
Modeling and Minimization of Interconnect Energy Dissipation in Nanometer Technologies.
DAC 2001: 754-757 |
| 74 | EE | Kanishka Lahiri,
Sujit Dey,
Anand Raghunathan:
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures.
VLSI Design 2001: 29-35 |
| 73 | EE | Debashis Panigrahi,
Sujit Dey,
Ramesh R. Rao,
Kanishka Lahiri,
Carla-Fabiana Chiasserini,
Anand Raghunathan:
Battery Life Estimation of Mobile Embedded Systems.
VLSI Design 2001: 57-63 |
| 72 | | Anand Raghunathan,
Sujit Dey:
Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies.
VLSI Design 2001: 9-10 |
| 71 | EE | Xiaoliang Bai,
Sujit Dey:
High-level Crosstalk Defect Simulation for System-on-Chip Interconnects.
VTS 2001: 169-177 |
| 70 | EE | Li Chen,
Sujit Dey:
Software-based self-testing methodology for processor cores.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(3): 369-380 (2001) |
| 69 | EE | Kanishka Lahiri,
Anand Raghunathan,
Sujit Dey:
System-level performance analysis for designing on-chipcommunication architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 768-783 (2001) |
| 2000 |
|---|
| 68 | EE | Kwang-Ting Cheng,
Sujit Dey,
Mike Rodgers,
Kaushik Roy:
Test challenges for deep sub-micron technologies.
DAC 2000: 142-149 |
| 67 | EE | Kanishka Lahiri,
Anand Raghunathan,
Ganesh Lakshminarayana,
Sujit Dey:
Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips.
DAC 2000: 513-518 |
| 66 | EE | Xiaoliang Bai,
Sujit Dey,
Janusz Rajski:
Self-test methodology for at-speed test of crosstalk in chip interconnects.
DAC 2000: 619-624 |
| 65 | EE | Li Chen,
Sujit Dey,
Pablo Sanchez,
Krishna Sekar,
Ying Cheng:
Embedded hardware and software self-testing methodologies for processor cores.
DAC 2000: 625-630 |
| 64 | EE | Marcello Lajolo,
Anand Raghunathan,
Sujit Dey,
Luciano Lavagno:
Efficient Power Co-Estimation Techniques for System-on-Chip Design.
DATE 2000: 27-34 |
| 63 | | Yervant Zorian,
Sujit Dey,
Mike Rodgers:
Test of Future System-on-Chips.
ICCAD 2000: 392-398 |
| 62 | | Kanishka Lahiri,
Anand Raghunathan,
Sujit Dey:
Efficient Exploration of the SoC Communication Architecture Design Space.
ICCAD 2000: 424-430 |
| 61 | | Yi Zhao,
Sujit Dey:
Analysis of interconnect crosstalk defect coverage of test sets.
ITC 2000: 492-501 |
| 60 | EE | Kanishka Lahiri,
Sujit Dey,
Anand Raghunathan:
Performance Analysis of Systems with Multi-Channel Communication Architectures.
VLSI Design 2000: 530-537 |
| 59 | EE | Li Chen,
Sujit Dey:
DEFUSE: A Deterministic Functional Self-Test Methodology for Processors.
VTS 2000: 255-262 |
| 58 | EE | Sujit Dey,
Debashis Panigrahi,
Li Chen,
Clark N. Taylor,
Krishna Sekar,
Pablo Sanchez:
Using a Soft Core in a SoC Design: Experiences with picoJava.
IEEE Design & Test of Computers 17(3): 60-71 (2000) |
| 57 | EE | Indradeep Ghosh,
Sujit Dey,
Niraj K. Jha:
A fast and low-cost testing technique for core-based system-chips.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(8): 863-877 (2000) |
| 1999 |
|---|
| 56 | EE | Ganesh Lakshminarayana,
Anand Raghunathan,
Kamal S. Khouri,
Niraj K. Jha,
Sujit Dey:
Common-Case Computation: A High-Level Technique for Power and Performance Optimization.
DAC 1999: 56-61 |
| 55 | EE | Michael Cuviello,
Sujit Dey,
Xiaoliang Bai,
Yi Zhao:
Fault modeling and simulation for crosstalk in system-on-chip interconnects.
ICCAD 1999: 297-303 |
| 54 | EE | Kanishka Lahiri,
Anand Raghunathan,
Sujit Dey:
Fast performance analysis of bus-based system-on-chip communication architectures.
ICCAD 1999: 566-573 |
| 53 | | Kaushik Roy,
Anand Raghunathan,
Sujit Dey:
Low Power Design Methodologies for Systems-on-Chips.
VLSI Design 1999: 609 |
| 52 | | Yervant Zorian,
Erik Jan Marinissen,
Sujit Dey:
Testing Embedded-Core-Based System Chips.
IEEE Computer 32(6): 52-60 (1999) |
| 51 | EE | Ganesh Lakshminarayana,
Anand Raghunathan,
Niraj K. Jha,
Sujit Dey:
Power management in high-level synthesis.
IEEE Trans. VLSI Syst. 7(1): 7-15 (1999) |
| 50 | EE | Sujit Dey,
Anand Raghunathan,
Niraj K. Jha,
Kazutoshi Wakabayashi:
Controller-based power management for control-flow intensive designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(10): 1496-1508 (1999) |
| 49 | EE | Indradeep Ghosh,
Niraj K. Jha,
Sujit Dey:
A low overhead design for testability and test generation technique for core-based systems-on-a-chip.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1661-1676 (1999) |
| 48 | EE | Srimat T. Chakradhar,
Sujit Dey:
Resynthesis and retiming for optimum partial scan.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(5): 621-630 (1999) |
| 47 | EE | Anand Raghunathan,
Sujit Dey,
Niraj K. Jha:
Register transfer level power optimization with emphasis on glitch analysis and reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(8): 1114-1131 (1999) |
| 1998 |
|---|
| 46 | | Sujit Dey,
Anand Raghunathan,
Rabindra K. Roy:
Considering Testability during High-level Design (Embedded Tutorial).
ASP-DAC 1998: 205-210 |
| 45 | EE | Marcello Lajolo,
Anand Raghunathan,
Sujit Dey,
Luciano Lavagno,
Alberto L. Sangiovanni-Vincentelli:
A case study on modeling shared memory access effects during performance analysis of HW/SW systems.
CODES 1998: 117-121 |
| 44 | EE | Indradeep Ghosh,
Sujit Dey,
Niraj K. Jha:
A Fast and Low Cost Testing Technique for Core-Based System-on-Chip.
DAC 1998: 542-547 |
| 43 | EE | Sujit Dey,
Jacob A. Abraham,
Yervant Zorian:
High-level design validation and test.
ICCAD 1998: 3 |
| 42 | EE | Ganesh Lakshminarayana,
Anand Raghunathan,
Niraj K. Jha,
Sujit Dey:
Transforming control-flow intensive designs to facilitate power management.
ICCAD 1998: 657-664 |
| 41 | EE | Yervant Zorian,
Erik Jan Marinissen,
Sujit Dey:
Testing embedded-core based system chips.
ITC 1998: 130- |
| 40 | EE | Srivaths Ravi,
Indradeep Ghosh,
Rabindra K. Roy,
Sujit Dey:
Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits.
VLSI Design 1998: 193-198 |
| 39 | | Ganesh Lakshminarayana,
Anand Raghunathan,
Niraj K. Jha,
Sujit Dey:
A Power Management Methodology for High-Level Synthesis.
VLSI Design 1998: 24-19 |
| 38 | EE | Subhrajit Bhattacharya,
Sujit Dey,
Franc Brglez:
Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization.
ACM Trans. Design Autom. Electr. Syst. 3(2): 285-307 (1998) |
| 37 | EE | Sujit Dey,
Vijay Gangaram,
Miodrag Potkonjak:
A controller redesign technique to enhance testability of controller-data path circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(2): 157-168 (1998) |
| 1997 |
|---|
| 36 | EE | Anand Raghunathan,
Sujit Dey,
Niraj K. Jha,
Kazutoshi Wakabayashi:
Power Management Techniques for Control-Flow Intensive Designs.
DAC 1997: 429-434 |
| 35 | EE | Sujit Dey,
Surendra Bommu:
Performance analysis of a system of communicating processes.
ICCAD 1997: 590-597 |
| 34 | | Toshiharu Asaka,
Masaaki Yoshida,
Subhrajit Bhattacharya,
Sujit Dey:
H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs.
ITC 1997: 265-274 |
| 33 | | Indradeep Ghosh,
Niraj K. Jha,
Sujit Dey:
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems.
ITC 1997: 50-59 |
| 32 | EE | Sujit Dey,
Miodrag Potkonjak:
Nonscan design-for-testability techniques using RT-level design information.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(12): 1488-1506 (1997) |
| 1996 |
|---|
| 31 | EE | Kenneth D. Wagner,
Sujit Dey:
High-Level Synthesis for Testability: A Survey and Perspective.
DAC 1996: 131-136 |
| 30 | EE | Anand Raghunathan,
Sujit Dey,
Niraj K. Jha:
Glitch Analysis and Reduction in Register Transfer Level.
DAC 1996: 331-336 |
| 29 | EE | Anand Raghunathan,
Sujit Dey,
Niraj K. Jha:
Register-transfer level estimation techniques for switching activity and power consumption.
ICCAD 1996: 158-165 |
| 28 | EE | Anand Raghunathan,
Sujit Dey,
Niraj K. Jha,
Kazutoshi Wakabayashi:
Controller re-specification to minimize switching activity in controller/data path circuits.
ISLPED 1996: 301-304 |
| 27 | EE | Subhrajit Bhattacharya,
Sujit Dey:
H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads.
VTS 1996: 74-80 |
| 26 | EE | Subhrajit Bhattacharya,
Sujit Dey,
Franc Brglez:
Fast true delay estimation during high level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1088-1105 (1996) |
| 1995 |
|---|
| 25 | EE | Miodrag Potkonjak,
Sujit Dey,
Rabindra K. Roy:
Synthesis-for-testability using transformations.
ASP-DAC 1995 |
| 24 | EE | Miodrag Potkonjak,
Sujit Dey,
Kazutoshi Wakabayashi:
Design-for-debugging of application specific designs.
ICCAD 1995: 295-301 |
| 23 | EE | Sujit Dey,
Vijay Gangaram,
Miodrag Potkonjak:
A controller-based design-for-testability technique for controller-data path circuits.
ICCAD 1995: 534-540 |
| 22 | EE | Miodrag Potkonjak,
Sujit Dey,
Rabindra K. Roy:
Considering testability at behavioral level: use of transformations for partial scan cost minimization under timing and area constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(5): 531-546 (1995) |
| 21 | EE | Pranav Ashar,
Sujit Dey,
Sharad Malik:
Exploiting multicycle false paths in the performance optimization of sequential logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1067-1075 (1995) |
| 20 | EE | Miodrag Potkonjak,
Sujit Dey,
Rabindra K. Roy:
Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1141-1154 (1995) |
| 1994 |
|---|
| 19 | EE | Subhrajit Bhattacharya,
Sujit Dey,
Franc Brglez:
Clock Period Optimization During Resource Sharing and Assignment.
DAC 1994: 195-200 |
| 18 | EE | Miodrag Potkonjak,
Sujit Dey:
Optimizing Resource Utilization and Testability Using Hot Potato Techniques.
DAC 1994: 201-205 |
| 17 | EE | Subhrajit Bhattacharya,
Sujit Dey,
Franc Brglez:
Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications.
DAC 1994: 491-496 |
| 16 | EE | Srimat T. Chakradhar,
Sujit Dey:
Resynthesis and Retiming for Optimum Partial Scan.
DAC 1994: 87-93 |
| 15 | EE | Sujit Dey,
Miodrag Potkonjak:
Non-scan design-for-testability of RT-level data paths.
ICCAD 1994: 640-645 |
| 14 | EE | Subhrajit Bhattacharya,
Sujit Dey,
Franc Brglez:
Provably correct high-level timing analysis without path sensitization.
ICCAD 1994: 736-742 |
| 13 | | Sujit Dey,
Miodrag Potkonjak:
Transforming Behavioral Specifications to Facilitate Synthesis of Testable Designs.
ITC 1994: 184-193 |
| 1993 |
|---|
| 12 | EE | Srimat T. Chakradhar,
Sujit Dey,
Miodrag Potkonjak,
Steven G. Rothweiler:
Sequential Circuit Delay optimization Using Global Path Delays.
DAC 1993: 483-489 |
| 11 | EE | Zia Iqbal,
Miodrag Potkonjak,
Sujit Dey,
Alice C. Parker:
Critical Path Minimization Using Retiming and Algebraic Speed-Up.
DAC 1993: 573-577 |
| 10 | EE | Sujit Dey,
Miodrag Potkonjak,
Rabindra K. Roy:
Exploiting hardware sharing in high-level synthesis for partial scan optimization.
ICCAD 1993: 20-25 |
| 9 | | Miodrag Potkonjak,
Sujit Dey,
Zia Iqbal,
Alice C. Parker:
High Performance Embedded System Optimization Using Algebraic and Generalized Retiming Techniques.
ICCD 1993: 498-504 |
| 8 | EE | Subhrajit Bhattacharya,
Franc Brglez,
Sujit Dey:
Transformations and resynthesis for testability of RT-level control-data path specifications.
IEEE Trans. VLSI Syst. 1(3): 304-318 (1993) |
| 1992 |
|---|
| 7 | EE | Sujit Dey,
Miodrag Potkonjak,
Steven G. Rothweiler:
Performance optimization of sequential circuits by eliminating retiming bottlenecks.
ICCAD 1992: 504-509 |
| 6 | EE | Pranav Ashar,
Sujit Dey,
Sharad Malik:
Exploiting multi-cycle false paths in the performance optimization of sequential circuits.
ICCAD 1992: 510-517 |
| 1991 |
|---|
| 5 | | Sujit Dey,
Franc Brglez,
Gershon Kedem:
Partitioning Sequential Circuits for Logic Optimization.
ICCD 1991: 70-76 |
| 4 | | Sujit Dey,
Franc Brglez,
Gershon Kedem:
Identification and Resynthesis of Pipelines in Sequential Networks.
VLSI 1991: 439-449 |
| 1990 |
|---|
| 3 | EE | Sujit Dey,
Franc Brglez,
Gershon Kedem:
Corolla Based Circuit Partitioning and Resynthesis.
DAC 1990: 607-612 |
| 2 | | Sujit Dey,
Pradip K. Srimani:
A New Parallel Sorting Algorithm and its Efficient VLSI Implementation.
Comput. J. 33(3): 241-246 (1990) |
| 1988 |
|---|
| 1 | EE | Sujit Dey,
Pradip K. Srimani:
Parallel VLSI computation of all shortest paths in a graph.
ACM Conference on Computer Science 1988: 373-379 |
