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Anirudh Devgan Vis

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*2008
56EESachin S. Sapatnekar, Eshel Haritan, Kurt Keutzer, Anirudh Devgan, Desmond Kirkpatrick, Stephen Meier, Duaine Pryor, Tom Spyrou: Reinventing EDA with manycore processors. DAC 2008: 126-127
2007
55EEMurari Mani, Anirudh Devgan, Michael Orshansky, Yaping Zhan: A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1790-1802 (2007)
54EEAnand Ramalingam, Anirudh Devgan, David Z. Pan: Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce. J. Low Power Electronics 3(1): 28-35 (2007)
2006
53EEAnand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan: Robust analytical gate delay modeling for low voltage circuits. ASP-DAC 2006: 61-66
52EERajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester: Analytical yield prediction considering leakage/performance correlation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1685-1695 (2006)
2005
51EEFlorentin Dartu, Anirudh Devgan, Noel Menezes: Variability modeling and variability-aware design in deep submicron integrated circuits. ACM Great Lakes Symposium on VLSI 2005: 1
50EEKanak Agarwal, Dennis Sylvester, David Blaauw, Anirudh Devgan: Achieving continuous VT performance in a dual VT process. ASP-DAC 2005: 393-398
49EEDavid Blaauw, Anirudh Devgan, Farid N. Najm: Leakage power: trends, analysis and avoidance. ASP-DAC 2005
48EEAnand Ramalingam, Bin Zhang, Anirudh Devgan, David Z. Pan: Sleep transistor sizing using timing criticality and temporal currents. ASP-DAC 2005: 1094-1097
47EEMichael W. Beattie, Hui Zheng, Anirudh Devgan, Byron Krauter: Spatially distributed 3D circuit models. DAC 2005: 153-158
46EEMurari Mani, Anirudh Devgan, Michael Orshansky: An efficient algorithm for statistical minimization of total power under timing yield constraints. DAC 2005: 309-314
45EEMaha Nizam, Farid N. Najm, Anirudh Devgan: Power grid voltage integrity verification. ISLPED 2005: 239-244
44EERahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown: Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. ISQED 2005: 284-290
43EEAnirudh Devgan, Ruchir Puri, Sachin Sapatnaker, Tanay Karnik, Rajiv V. Joshi: Design of sub-90nm Circuits and Design Methodologies. ISQED 2005: 3-4
42EEAnirudh Devgan, Luca Daniel, Byron Krauter, Lei He: Modeling and Design of Chip-Package Interface. ISQED 2005: 6
41EEAnirudh Devgan, Sani R. Nassif: Power Variability and Its Impact on Design. VLSI Design 2005: 679-682
40EERajeev R. Rao, David Blaauw, Dennis Sylvester, Anirudh Devgan: Modeling and Analysis of Parametric Yield under Power and Performance Constraints. IEEE Design & Test of Computers 22(4): 376-385 (2005)
39EEEmrah Acar, Anirudh Devgan, Sani R. Nassif: Leakage and Leakage Sensitivity Computation for Combinational Circuits. J. Low Power Electronics 1(2): 172-181 (2005)
2004
38EERajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester: Parametric yield estimation considering leakage variability. DAC 2004: 442-447
37EECharles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan: Closed-form delay and slew metrics made easy. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1661-1669 (2004)
36EEChandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan: Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 509-516 (2004)
2003
35EECharles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan: Delay and slew metrics using the lognormal distribution. DAC 2003: 382-385
34EEJiayong Le, Lawrence T. Pileggi, Anirudh Devgan: Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics. ICCAD 2003: 491-496
33EEAnirudh Devgan, Chandramouli V. Kashyap: Block-based Static Timing Analysis with Uncertainty. ICCAD 2003: 607-614
32EERahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown: Efficient techniques for gate leakage estimation. ISLPED 2003: 100-103
31EEHaihua Su, Frank Liu, Anirudh Devgan, Emrah Acar, Sani R. Nassif: Full chip leakage estimation considering power supply and temperature variations. ISLPED 2003: 78-83
30EEEmrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns: Leakage and leakage sensitivity computation for combinational circuits. ISLPED 2003: 96-99
29EEChandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan: Closed form expressions for extending step delay and slew metrics to ramp inputs. ISPD 2003: 24-31
2002
28EEChandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan: PERI: a technique for extending delay and slew metrics to ramp inputs. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 57-62
27EECharles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay: Correction to "interconnect synthesis without wire tapering". IEEE Trans. on CAD of Integrated Circuits and Systems 21(4): 497-497 (2002)
2001
26EEHao Ji, Anirudh Devgan, Wayne Wei-Ming Dai: KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect. ASP-DAC 2001: 379-384
25EECharles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay: Interconnect synthesis without wire tapering. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 90-104 (2001)
24EECharles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap: RC delay metrics for performance optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 571-582 (2001)
2000
23 Anirudh Devgan, Hao Ji, Wayne Wei-Ming Dai: How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K. ICCAD 2000: 150-155
22 Chandramouli V. Kashyap, Charles J. Alpert, Anirudh Devgan: An "Effective" Capacitance Based Delay Metric for RC Interconnect. ICCAD 2000: 229-234
21EECharles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap: A two moment RC delay metric for performance optimization. ISPD 2000: 69-74
20EETuyen V. Nguyen, Anirudh Devgan, Ognen J. Nastov, David W. Winston: Transient sensitivity computation in controlled explicit piecewiselinear simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 98-110 (2000)
1999
19EECharles J. Alpert, Anirudh Devgan, Stephen T. Quay: Buffer Insertion with Accurate Gate and Interconnect Delay Computation. DAC 1999: 479-484
18EEAnirudh Devgan, Peter R. O'Brien: Realizable reduction for RC interconnect circuits. ICCAD 1999: 204-207
17EECharles J. Alpert, Anirudh Devgan, Stephen T. Quay: Is wire tapering worthwhile? ICCAD 1999: 430-436
16EECharles J. Alpert, Anirudh Devgan, Stephen T. Quay: Buffer insertion for noise and delay optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1633-1645 (1999)
1998
15 Anirudh Devgan, Sandip Kundu: Timing Analysis and Optimization: From Devices to Systems (Abstract of Embedded Tutorial). ASP-DAC 1998: 345
14EECharles J. Alpert, Anirudh Devgan, Stephen T. Quay: Buffer Insertion for Noise and Delay Optimization. DAC 1998: 362-367
13EETuyen V. Nguyen, Anirudh Devgan, Ognen J. Nastov: Adjoint Transient Sensitivity Computation in Piecewise Linear Simulation. DAC 1998: 477-482
12EETuyen V. Nguyen, Anirudh Devgan, Ali Sadigh: Simulation of coupling capacitances using matrix partitioning. ICCAD 1998: 12-18
1997
11EECharles J. Alpert, Anirudh Devgan: Wire Segmenting for Improved Buffer Insertion. DAC 1997: 588-593
10EEAnirudh Devgan: Efficient coupled noise estimation for on-chip interconnects. ICCAD 1997: 147-151
9EETuyen V. Nguyen, Anirudh Devgan: State transformation in event driven explicit simulation. ICCAD 1997: 289-294
8EEAnirudh Devgan, Leon Stok, Sandip Kundu: Timing analysis and optimization: from devices to systems (tutorial). ICCAD 1997
1996
7EEAnirudh Devgan: Transient simulation of integrated circuits in the charge-voltage plane. IEEE Trans. on CAD of Integrated Circuits and Systems 15(11): 1379-1390 (1996)
1995
6EEAnirudh Devgan: Efficient and accurate transient simulation in charge-voltage plane. ICCAD 1995: 110-114
5EEAnirudh Devgan: Accurate device modeling techniques for efficient timing simulation of integrated circuits. ICCD 1995: 138-143
4EEAnirudh Devgan, Ronald A. Rohrer: Efficient simulation of interconnect and mixed analog-digital circuits in ACES. VLSI Design 1995: 229-233
1994
3EEAnirudh Devgan, Ronald A. Rohrer: Adaptively controlled explicit simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 13(6): 746-762 (1994)
1993
2EEAnirudh Devgan, Ronald A. Rohrer: Event driven adaptively controlled explicit simulation of integrated circuits. ICCAD 1993: 136-140
1 Anirudh Devgan, Ronald A. Rohrer: ACES: A Transient Simulation Strategy for Integrated Circuits. ICCD 1993: 357-360

Coauthor Index

1Emrah Acar [30] [31] [39]
2Kanak Agarwal [44] [50]
3Charles J. Alpert [11] [14] [16] [17] [19] [21] [22] [24] [25] [27] [28] [29] [35] [36] [37]
4Michael W. Beattie [47]
5David Blaauw (David T. Blaauw) [38] [40] [49] [50] [52]
6Richard B. Brown [32] [44]
7Jeffrey L. Burns [30] [32]
8Wayne Wei-Ming Dai [23] [26]
9Luca Daniel [42]
10Florentin Dartu [51]
11John P. Fishburn [25] [27]
12Eshel Haritan [56]
13Lei He [42]
14Hao Ji [23] [26]
15Rajiv V. Joshi [43]
16Tanay Karnik [43]
17Chandramouli V. Kashyap [21] [22] [24] [28] [29] [33] [35] [36] [37]
18Kurt Keutzer [56]
19Desmond Kirkpatrick [56]
20Sreekumar V. Kodakara [53]
21Byron Krauter [42] [47]
22Sandip Kundu [8] [15]
23Jiayong Le [34]
24Frank Liu [28] [29] [31] [35] [36] [37]
25Ying Liu [30]
26Murari Mani [46] [55]
27Stephen Meier [56]
28Noel Menezes [51]
29Farid N. Najm [45] [49]
30Sani R. Nassif [30] [31] [39] [41]
31Ognen J. Nastov [13] [20]
32Tuyen V. Nguyen [9] [12] [13] [20]
33Maha Nizam [45]
34Kevin J. Nowka [44]
35Peter R. O'Brien [18]
36Michael Orshansky [46] [55]
37David Z. Pan (David Zhigang Pan) [48] [53] [54]
38Lawrence T. Pileggi (Larry T. Pileggi, Lawrence T. Pillage) [34]
39Duaine Pryor [56]
40Ruchir Puri [43]
41Stephen T. Quay [14] [16] [17] [19] [25] [27]
42Anand Ramalingam [48] [53] [54]
43Rahul M. Rao [30] [32] [44]
44Rajeev R. Rao [38] [40] [52]
45Ronald A. Rohrer [1] [2] [3] [4]
46Ali Sadigh [12]
47Sachin Sapatnaker [43]
48Sachin S. Sapatnekar [56]
49Tom Spyrou [56]
50Leon Stok [8]
51Haihua Su [30] [31]
52Dennis Sylvester [38] [40] [44] [50] [52]
53David W. Winston [20]
54Yaping Zhan [55]
55Bin Zhang [48]
56Hui Zheng [47]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)