dblp.uni-trier.dewww.uni-trier.de

Jérémie Detrey Vis

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeerX - CSB - MetaPress - Google - Bing - Yahoo

*2009
16EEJean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals, Eiji Okamoto, Francisco Rodríguez-Henríquez: Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers. CHES 2009: 225-239
2008
15EEFlorent de Dinechin, Jérémie Detrey, Octavian Cret, Radu Tudoran: When FPGAs are better at floating-point than microprocessors. FPGA 2008: 260
14EEJean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto, Francisco Rodríguez-Henríquez: A Comparison between Hardware Accelerators for the Modified Tate Pairing over F2m and F3m. Pairing 2008: 297-315
13EEJean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto, Masaaki Shirase, Tsuyoshi Takagi: Algorithms and Arithmetic Operators for Computing the etaT Pairing in Characteristic Three. IEEE Trans. Computers 57(11): 1454-1468 (2008)
12EEJérémie Detrey, Florent de Dinechin: Fonctions élémentaires en virgule flottante pour les accélérateurs reconfigurables. Technique et Science Informatiques 27(6): 673-698 (2008)
2007
11EEJean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto: Arithmetic Operators for Pairing-Based Cryptography. CHES 2007: 239-255
10EEJérémie Detrey, Florent de Dinechin: Floating-Point Trigonometric Functions for FPGAs. FPL 2007: 29-34
9EEJérémie Detrey, Florent de Dinechin, Xavier Pujol: Return of the hardware floating-point elementary function. IEEE Symposium on Computer Arithmetic 2007: 161-168
8EEJérémie Detrey, Florent de Dinechin: Parameterized floating-point logarithm and exponential functions for FPGAs. Microprocessors and Microsystems 31(8): 537-545 (2007)
7EEJérémie Detrey, Florent de Dinechin: A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic. VLSI Signal Processing 49(1): 161-175 (2007)
2006
6EESylvain Collange, Jérémie Detrey, Florent de Dinechin: Floating Point or LNS: Choosing the Right Arithmetic on an Aapplication Basis. DSD 2006: 197-203
2005
5EEJérémie Detrey, Florent de Dinechin: Table-based polynomials for fast hardware function evaluation. ASAP 2005: 328-333
4 Jérémie Detrey, Florent de Dinechin: A Parameterized Floating-Point Exponential Function for FPGAs. FPT 2005: 27-34
3EEJérémie Detrey, Florent de Dinechin: Outils pour une comparaison sans a priori entre arithmétique logarithmique et arithmétique flottante. Technique et Science Informatiques 24(6): 625-643 (2005)
2004
2EEJérémie Detrey, Florent de Dinechin: Second Order Function Approximation Using a Single Multiplication on FPGAs. FPL 2004: 221-230
2002
1EEJérémie Detrey, Florent de Dinechin: Multipartite Tables in JBits for the Evaluation of Functions on FPGAs. IPDPS 2002

Coauthor Index

1Jean-Luc Beuchat [11] [13] [14] [16]
2Nicolas Brisebarre [11] [13] [14]
3Sylvain Collange [6]
4Octavian Cret [15]
5Florent de Dinechin [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [12] [15]
6Nicolas Estibals [16]
7Eiji Okamoto [11] [13] [14] [16]
8Xavier Pujol [9]
9Francisco Rodríguez-Henríquez [14] [16]
10Masaaki Shirase [13]
11Tsuyoshi Takagi [13]
12Radu Tudoran [15]

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)