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Edward S. Davidson Vis

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*2008
81EEMichel N. Victor, Aris K. Silzars, Edward S. Davidson: A freespace crossbar for multi-core processors. ICS 2008: 56-62
2004
80EEMikhail Smelyanskiy, Scott A. Mahlke, Edward S. Davidson: Probabilistic Predicate-Aware Modulo Scheduling. CGO 2004: 151-162
79EEViji Srinivasan, Edward S. Davidson, Gary S. Tyson: A Prefetch Taxonomy. IEEE Trans. Computers 53(2): 126-140 (2004)
2003
78EEMikhail Smelyanskiy, Scott A. Mahlke, Edward S. Davidson, Hsien-Hsin S. Lee: Predicate-Aware Scheduling: A Technique for Reducing Resource Constraints. CGO 2003: 169-178
77EEMurali Annavaram, Jignesh M. Patel, Edward S. Davidson: Call graph prefetching for database applications. ACM Trans. Comput. Syst. 21(4): 412-444 (2003)
2002
76EEStevan A. Vlaovic, Edward S. Davidson: TAXI: Trace Analysis for X86 Interpretation. ICCD 2002: 508-514
75EEStevan A. Vlaovic, Edward S. Davidson: Boosting trace cache performance with nonhead miss speculation. ICS 2002: 179-188
2001
74EEMurali Annavaram, Jignesh M. Patel, Edward S. Davidson: Call Graph Prefetching for Database Applications. HPCA 2001: 281-
73EEViji Srinivasan, Edward S. Davidson, Gary S. Tyson, Mark J. Charney, Thomas R. Puzak: Branch History Guided Instruction Prefetching. HPCA 2001: 291-300
72 Edward S. Tam, Stevan A. Vlaovic, Gary S. Tyson, Edward S. Davidson: Allocation by Conflict: A Simple Effective Multilateral Cache Management Scheme. ICCD 2001: 133-141
71EEMurali Annavaram, Jignesh M. Patel, Edward S. Davidson: Data prefetching by dependence graph precomputation. ISCA 2001: 52-61
70EEG. X. Tyson, M. Smelyanskyi, Edward S. Davidson: Evaluating the Use of Register Queues in Software Pipelined Loops. IEEE Trans. Computers 50(8): 769-783 (2001)
2000
69EEMikhail Smelyanskiy, Gary S. Tyson, Edward S. Davidson: Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining. IEEE PACT 2000: 3-12
68EEStevan A. Vlaovic, Edward S. Davidson, Gary S. Tyson: Improving BTB performance in the presence of DLLs. MICRO 2000: 77-86
1999
67EEWaleed Meleis, Edward S. Davidson: Dual-Issue Scheduling with Spills for Binary Trees. SODA 1999: 678-686
66EEEdward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson: Active Management of Data Caches by Exploiting Reuse Information. IEEE Trans. Computers 48(11): 1244-1259 (1999)
1998
65EEJanak H. Patel, Edward S. Davidson: Improving the Throughput of a Pipeline by Insertion of Delays. 25 Years ISCA: Retrospectives and Reprints 1998: 132-137
64EEDavid J. Kuck, Edward S. Davidson, Duncan H. Lawrie, Ahmed H. Sameh, Chuan-Qi Zhu: The Cedar System and an Initial Performance Study. 25 Years ISCA: Retrospectives and Reprints 1998: 462-472
63EEAlexander V. Veidenbaum, Pen-Chung Yew, David J. Kuck, Constantine D. Polychronopoulos, David A. Padua, Edward S. Davidson, Kyle Gallivan: Retrospective: The Cedar System. 25 Years ISCA: Retrospectives and Reprints 1998: 89-91
62EEGheith A. Abandah, Edward S. Davidson: Origin 2000 Design Enhancements for Communication Intensive Applications. IEEE PACT 1998: 30-39
61EEGheith A. Abandah, Edward S. Davidson: Configuration Independent Analysis for Characterizing Shared-Memory Applications. IPPS/SPDP 1998: 485-491
60EEGheith A. Abandah, Edward S. Davidson: Effects of Architectural and Technological Advances on the HP/Convex Exemplar's Memory and Communication Performance. ISCA 1998: 318-329
59EEJude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, Matthew K. Farrens: Utilizing Reuse Information in Data Cache Management. International Conference on Supercomputing 1998: 449-456
58EEEdward S. Tam, Jude A. Rivers, Gary S. Tyson, Edward S. Davidson: mlcache: A Flexible Multi-Lateral Cache Simulator. MASCOTS 1998: 19-26
57EEGheith A. Abandah, Edward S. Davidson: Characterizing Distributed Shared Memory Performance: A Case Study of the Convex SPP1000. IEEE Trans. Parallel Distrib. Syst. 9(2): 206-216 (1998)
1997
56 Jude A. Rivers, Edward S. Tam, Edward S. Davidson: On Effective Data Supply For Multi-Issue Processors. ICCD 1997: 519-528
55EEJude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin: On High-Bandwidth Data Cache Design for Multi-Issue Processors. MICRO 1997: 46-56
54 Alexandre E. Eichenberger, Edward S. Davidson: Efficient Formulation for Optimal Modulo Schedulers. PLDI 1997: 194-205
1996
53 Jude A. Rivers, Edward S. Davidson: Reducing Conflicts in Direct-Mapped Caches with a Temporality-Based Design. ICPP, Vol. 1 1996: 154-163
52EEGheith A. Abandah, Edward S. Davidson: Modeling the Communication Performance of the IBM SP2. IPPS 1996: 249-257
51EEKaren A. Tomko, Edward S. Davidson: Profile Driven Weighted Decomposition. International Conference on Supercomputing 1996: 165-172
50 Alexandre E. Eichenberger, Edward S. Davidson: A Reduced Multipipeline Machine Description that Preserves Scheduling Constraints. PLDI 1996: 12-22
49 Jude A. Rivers, Edward S. Davidson: Performance Issues in Integrating Temporality-Based Caching with Prefetching. Perform. Eval. 27/28(4): 189-207 (1996)
1995
48EEJohn-David Wellman, Edward S. Davidson: The resource conflict methodology for early-stage design space exploration of superscalar RISC processors. ICCD 1995: 110-
47EEAlexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham: Optimum Modulo Schedules for Minimum Register Requirements. International Conference on Supercomputing 1995: 31-40
46EEAlexandre E. Eichenberger, Edward S. Davidson: Register allocation for predicated code. MICRO 1995: 180-191
45EEAlexandre E. Eichenberger, Edward S. Davidson: Stage scheduling: a technique to reduce the register requirements of a modulo schedule. MICRO 1995: 338-349
44EEChuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah: Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability. IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1526-1545 (1995)
1994
43 Tien-Pao Shih, Edward S. Davidson: Grouping Array Layouts to Reduce Communication and Improve Locality of Parallel Programs. ICPADS 1994: 558-566
42 Eric L. Boyd, Waqar Azeem, Hsien-Hsin S. Lee, Tien-Pao Shih, Shih-Hao Hung, Edward S. Davidson: A Hierarchical Approach to Modeling and Improving the Performance of Scientific Applications on the KSR1. ICPP (3) 1994: 188-192
41EEWaleed Meleis, Edward S. Davidson: Optimal local register allocation for a multiple-issue machine. International Conference on Supercomputing 1994: 107-116
40EEEric L. Boyd, Edward S. Davidson: Communication in the KSR1 MPP: performance evaluation using synthetic workload experiments. International Conference on Supercomputing 1994: 166-175
39EEAlexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham: Minimum register requirements for a modulo schedule. MICRO 1994: 75-84
1993
38 Daniel Windheiser, Eric L. Boyd, Eric Hao, Santosh G. Abraham, Edward S. Davidson: KSR 1 Multiprocessor: Analysis of Latency Hiding Techniques in a Sparse Solver. IPPS 1993: 454-461
37 Eric L. Boyd, Edward S. Davidson: Hierarchical Performance Modeling with MACS: A Case Study of the Convex C-240. ISCA 1993: 203-212
36 David J. Kuck, Edward S. Davidson, Duncan H. Lawrie, Ahmed H. Sameh, Chuan-Qi Zhu, Alexander V. Veidenbaum, Jeff Konicek, Pen-Chung Yew, Kyle Gallivan, William Jalby, Harry A. G. Wijshoff, Randall Bramley, U. M. Yang, Perry A. Emrath, David A. Padua, Rudolf Eigenmann, Jay Hoeflinger, Greg Jaxon, Zhiyuan Li, T. Murphy, John T. Andrews, Stephen W. Turner: The Cedar System and an Initial Performance Study. ISCA 1993: 213-223
35EEEric L. Boyd, John-David Wellman, Santosh G. Abraham, Edward S. Davidson: Evaluating the Communication Performance of MPPs Using Synthetic Sparse Matrix Multiplication Workloads. International Conference on Supercomputing 1993: 240-250
34EEKarem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson: Synchronization of pipelines. IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1132-1146 (1993)
1992
33EEChuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah: Using constraint geometry to determine maximum rate pipeline clocking. ICCAD 1992: 142-148
32EEWilliam H. Mangione-Smith, Santosh G. Abraham, Edward S. Davidson: Register requirements of pipelined processors. ICS 1992: 260-271
1991
31 William H. Mangione-Smith, Santosh G. Abraham, Edward S. Davidson: Vector Register Design for Polycyclic Vector Scheduling. ASPLOS 1991: 154-163
30 Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson: Optimal Clocking of Circular Pipelines. ICCD 1991: 642-650
29 Jeff Konicek, Tracy Tilton, Alexander V. Veidenbaum, Chuan-Qi Zhu, Edward S. Davidson, Ruppert A. Downing, Michael J. Haney, Manish Sharma, Pen-Chung Yew, P. Michael Farmwald, David J. Kuck, Daniel M. Lavery, Robert A. Lindsey, D. Pointer, John T. Andrews, Thomas Beck, T. Murphy, Stephen W. Turner, Nancy J. Warter: The Organization of the Cedar System. ICPP (1) 1991: 49-56
28 William H. Mangione-Smith, Santosh G. Abraham, Edward S. Davidson: A Performance Comparison of the IBM RS/6000 and the Astronautics ZS-1. IEEE Computer 24(1): 39-46 (1991)
1988
27EEJ. H. Tang, Edward S. Davidson: An evaluation of Cray X-MP performance on vectorizable Livermore FORTRAN kernels. ICS 1988: 510-518
26 Geoffrey D. McNiven, Edward S. Davidson: Analysis of Memory Referencing Behavior For Design of Local Memories. ISCA 1988: 56-63
25EEJ. H. Tang, Edward S. Davidson, J. Tong: Polycyclic Vector scheduling vs. Chaining on 1-Port Vector supercomputers. SC 1988: 122
24 Timothy A. Davis, Edward S. Davidson: Pairwise Reduction for the Direct, Parallel Solution of Sparse, Unsymmetric Sets of Linear Equations. IEEE Trans. Computers 37(12): 1648-1654 (1988)
1987
23 Timothy A. Davis, Edward S. Davidson: PSOLVE : A Concurrent Algorithm for Solving Sparse Systems of Linear Equations. ICPP 1987: 483-490
22 Philip G. Emma, Edward S. Davidson: Characterization of Branch and Data Dependencies in Programs for Evaluating Pipeline Performance. IEEE Trans. Computers 36(7): 859-875 (1987)
1986
21 Andrew R. Pleszkun, Gurindar S. Sohi, Bassam Z. Kahhaleh, Edward S. Davidson: Features of the Structured Memory Access (SMA) Architecture. COMPCON 1986: 259-265
20 Edward S. Davidson: A Broader Range of Possible Answers to the Issues Raised by RISC. COMPCON 1986: 313-315
19 Santosh G. Abraham, Edward S. Davidson: A Communication Model for Optimizing Hierarchical Multiprocessor Systems. ICPP 1986: 467-474
18 Peter Y.-T. Hsu, Edward S. Davidson: Highly Concurrent Scalar Processing. ISCA 1986: 386-395
1985
17 Peter Y.-T. Hsu, Joseph T. Rahmeh, Edward S. Davidson, Jacob A. Abraham: TIDBITS: Speedup Via Time-Delay Bit-Slicing in ALU Design for VLSI Technology. ISCA 1985: 28-35
16 Gurindar S. Sohi, Edward S. Davidson, Janak H. Patel: An Efficient LISP-Execution Architecture with a New Representation for List Structures. ISCA 1985: 91-98
1984
15 Pradip Bose, Edward S. Davidson: Design of Instruction Set Architectures for Support of High-Level Languages . ISCA 1984: 198-206
1983
14 Andrew R. Pleszkun, Edward S. Davidson: Structured Memory Access Architecture. ICPP 1983: 461-471
13 Phil C. C. Yeh, Janak H. Patel, Edward S. Davidson: Performance of Shared Cache for Parallel-Pipelined Computer Systems ISCA 1983: 117-123
12 Phil C. C. Yeh, Janak H. Patel, Edward S. Davidson: Shared Cache for Multiple-Stream Computer Systems. IEEE Trans. Computers 32(1): 38-47 (1983)
1982
11EEEdward S. Davidson: Evaluating database management systems. AFIPS National Computer Conference 1982: 639-648
10 David W. L. Yen, Janak H. Patel, Edward S. Davidson: Memory Interference in Synchronous Multiprocessor Systems. IEEE Trans. Computers 31(11): 1116-1121 (1982)
1981
9 Robert L. Budzinski, Edward S. Davidson, Wataru Mayeda, Harold S. Stone: DMIN: An Algorithm for Computing the Optimal Dynamic Allocation in a Virtual Memory Computer. IEEE Trans. Software Eng. 7(1): 113-121 (1981)
8 Robert L. Budzinski, Edward S. Davidson: A Comparison of Dynamic and Static Virtual Memory Allocation Algorithms. IEEE Trans. Software Eng. 7(1): 122-131 (1981)
1980
7 Edward S. Davidson: A Multiple Stream Microprocessor Prototype System: AMP-1. ISCA 1980: 9-16
6 B. Kumar, Edward S. Davidson: Computer System Design Using a Hierarchical Approach to Performance Evaluation. Commun. ACM 23(9): 511-521 (1980)
1978
5 B. Kumar, Edward S. Davidson: Performance Evaluation of Highly Concurrent Computers by Deterministic Simulation. Commun. ACM 21(11): 904-913 (1978)
1977
4 Dan W. Hammerstrom, Edward S. Davidson: Information Content of CPU Memory Referencing Behavior. ISCA 1977: 184-192
3 Faye A. Briggs, Edward S. Davidson: Organization of Semiconductor Memories for Parallel-Pipelined Processors. IEEE Trans. Computers 26(2): 162-169 (1977)
1976
2 Janak H. Patel, Edward S. Davidson: Improving the Throughput of a Pipeline by Insertion of Delays. ISCA 1976: 159-164
1974
1 Daniel L. Weller, Edward S. Davidson: Optimal Searching Algorihtms for Parallel Pipelined Computers. Sagamore Computer Conference 1974: 291-305

Coauthor Index

1Gheith A. Abandah [52] [57] [60] [61] [62]
2Jacob A. Abraham [17]
3Santosh G. Abraham [19] [28] [31] [32] [35] [38] [39] [47]
4John T. Andrews [29] [36]
5Murali Annavaram [71] [74] [77]
6Todd M. Austin [55]
7Waqar Azeem [42]
8Thomas Beck [29]
9Pradip Bose [15]
10Eric L. Boyd [35] [37] [38] [40] [42]
11Randall Bramley [36]
12Faye A. Briggs [3]
13Robert L. Budzinski [8] [9]
14Timothy M. Burks [30] [34]
15Chuan-Hua Chang [33] [44]
16Mark J. Charney [73]
17Timothy A. Davis [23] [24]
18Ruppert A. Downing [29]
19Alexandre E. Eichenberger [39] [45] [46] [47] [50] [54]
20Rudolf Eigenmann [36]
21Philip G. Emma [22]
22Perry A. Emrath [36]
23P. Michael Farmwald [29]
24Matthew K. Farrens [59]
25Kyle A. Gallivan (Kyle Gallivan) [36] [63]
26Dan W. Hammerstrom [4]
27Michael J. Haney [29]
28Eric Hao [38]
29Jay Hoeflinger [36]
30Peter Y.-T. Hsu [17] [18]
31Shih-Hao Hung [42]
32William Jalby [36]
33Greg Jaxon [36]
34Bassam Z. Kahhaleh [21]
35Jeff Konicek [29] [36]
36David J. Kuck [29] [36] [63] [64]
37B. Kumar [5] [6]
38Daniel M. Lavery [29]
39Duncan H. Lawrie [36] [64]
40Hsien-Hsin S. Lee [42] [78]
41Zhiyuan Li [36]
42Robert A. Lindsey [29]
43Scott A. Mahlke [78] [80]
44William H. Mangione-Smith [28] [31] [32]
45Wataru Mayeda [9]
46Geoffrey D. McNiven [26]
47Waleed Meleis [41] [67]
48Trevor N. Mudge [30] [34]
49T. Murphy [29] [36]
50David A. Padua [36] [63]
51Janak H. Patel [2] [10] [12] [13] [16] [65]
52Jignesh M. Patel [71] [74] [77]
53Andrew R. Pleszkun [14] [21]
54D. Pointer [29]
55Constantine D. Polychronopoulos [63]
56Thomas R. Puzak [73]
57Joseph T. Rahmeh [17]
58Jude A. Rivers [49] [53] [55] [56] [58] [59] [66]
59Karem A. Sakallah [30] [33] [34] [44]
60Ahmed H. Sameh [36] [64]
61Manish Sharma [29]
62Tien-Pao Shih [42] [43]
63Aris K. Silzars [81]
64Mikhail Smelyanskiy [69] [78] [80]
65M. Smelyanskyi [70]
66Gurindar S. Sohi [16] [21]
67Vijayalakshmi Srinivasan [66]
68Viji Srinivasan [73] [79]
69Harold S. Stone [9]
70Edward S. Tam [56] [58] [59] [66] [72]
71J. H. Tang [25] [27]
72Tracy Tilton [29]
73Karen A. Tomko [51]
74J. Tong [25]
75Stephen W. Turner [29] [36]
76G. X. Tyson [70]
77Gary S. Tyson [55] [58] [59] [66] [68] [69] [72] [73] [79]
78Alexander V. Veidenbaum [29] [36] [63]
79Michel N. Victor [81]
80Stevan A. Vlaovic [68] [72] [75] [76]
81Nancy J. Warter [29]
82Daniel L. Weller [1]
83John-David Wellman [35] [48]
84Harry A. G. Wijshoff [36]
85Daniel Windheiser [38]
86U. M. Yang [36]
87Phil C. C. Yeh [12] [13]
88David W. L. Yen [10]
89Pen-Chung Yew [29] [36] [63]
90Chuanqi Zhu (Chuan-Qi Zhu) [29] [36] [64]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)