Shidhartha Das Vis

*	2009
7	EE	Shidhartha Das, David Blaauw, David Bull, Krisztián Flautner, Rob Aitken: Addressing design margins through error-tolerant circuits. DAC 2009: 11-12
	2008
6	EE	Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott A. Mahlke, David Bull: DVFS in loop accelerators using BLADES. DAC 2008: 894-897
	2004
5	EE	Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David Blaauw, Trevor N. Mudge: Circuit-aware architectural simulation. DAC 2004: 305-310
4	EE	Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David Blaauw, Trevor N. Mudge: Reducing pipeline energy demands with local DVS and dynamic retiming. ISLPED 2004: 319-324
3	EE	Dan Ernst, Shidhartha Das, Seokwoo Lee, David Blaauw, Todd M. Austin, Trevor N. Mudge, Nam Sung Kim, Krisztián Flautner: Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation. IEEE Micro 24(6): 10-20 (2004)
	2003
2	EE	Shidhartha Das, Kanak Agarwal, David Blaauw, Dennis Sylvester: Optimal Inductance for On-chip RLC Interconnections. ICCD 2003: 264-
1	EE	Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge: Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. MICRO 2003: 7-18

Coauthor Index

1	Kanak Agarwal	[2]
2	Robert C. Aitken (Rob Aitken)	[7]
3	Todd M. Austin	[1] [3] [4] [5]
4	Valeria Bertacco	[5]
5	David Blaauw (David T. Blaauw)	[1] [2] [3] [4] [5] [7]
6	David Bull	[6] [7]
7	Ganesh S. Dasika	[6]
8	Dan Ernst	[1] [3]
9	Kevin Fan	[6]
10	Krisztián Flautner	[1] [3] [7]
11	Nam Sung Kim	[1] [3]
12	Seokwoo Lee	[3] [4] [5]
13	Scott A. Mahlke	[6]
14	Trevor N. Mudge	[1] [3] [4] [5]
15	Sanjay Pant	[1]
16	Toan Pham	[1] [4]
17	Rajeev R. Rao	[1]
18	Dennis Sylvester	[2]
19	Conrad H. Ziesler	[1]