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Jason Cong Vis

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*2009
237EEJason Cong, Puneet Gupta, John Lee: On the futility of statistical power optimization. ASP-DAC 2009: 167-172
236EEJason Cong, Guojie Luo: A multilevel analytical placement for 3D ICs. ASP-DAC 2009: 361-366
235EEJason Cong, Albert Liu, Bin Liu: A variation-tolerant scheduler for better than worst-case behavioral synthesis. CODES+ISSS 2009: 221-228
234EEJason Cong, N. S. Nagaraj, Ruchir Puri, William H. Joyner, Jeff Burns, Moshe Gavrielov, Riko Radojcic, Peter Rickert, Hans Stork: Moore's Law: another casualty of the financial meltdown? DAC 2009: 202-203
233EERuchir Puri, Eshel Haritan, Stan Krolikoski, Jason Cong, Tim Kogel, Bradley D. McCredie, John Shen, Andrés Takach: From milliwatts to megawatts: system level power challenge. DAC 2009: 750-751
232EEJason Cong, Karthik Gururaj: Energy efficient multiprocessor task scheduling under input-dependent variation. DATE 2009: 411-416
231EEJason Cong, Karthik Gururaj, Guoling Han: Synthesis of reconfigurable high-performance multicore systems. FPGA 2009: 201-208
230EEJason Cong, Karthik Gururaj, Bin Liu, Chunyue Liu, Yi Zou, Zhiru Zhang, Sheng Zhou: Revisiting bitwidth optimizations. FPGA 2009: 278
229EEAlexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu: High-performance CUDA kernel execution on FPGAs. ICS 2009: 515-516
228EEJason Cong, Yiping Fan, Junjuan Xu: Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture. ACM Trans. Design Autom. Electr. Syst. 14(3): (2009)
2008
227EECheng-Tao Hsieh, Jason Cong, Zhiru Zhang, Shih-Chieh Chang: Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA. ASP-DAC 2008: 10-15
226EEXin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong: LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. ASP-DAC 2008: 209-212
225EEWei Jiang, Zhiru Zhang, Miodrag Potkonjak, Jason Cong: Scheduling with integer time budgeting for low-power optimization. ASP-DAC 2008: 22-27
224EEJason Cong, Junjuan Xu: Simultaneous FU and Register Binding Based on Network Flow Method. DATE 2008: 1057-1062
223EEJason Cong, Wei Jiang: Pattern-based behavior synthesis for FPGA resource reduction. FPGA 2008: 107-116
222EEKirill Minkovich, Jason Cong: Mapping for better than worst-case delays in LUT-based FPGA designs. FPGA 2008: 56-64
221EEJason Cong, Yi Zou: Lithographic aerial image simulation with FPGA-based hardwareacceleration. FPGA 2008: 67-76
220EEM. Frank Chang, Jason Cong, Adam Kaplan, Mishali Naik, Glenn Reinman, Eran Socher, Sai-Wang Tam: CMP network-on-chip overlaid with multi-band RF-interconnect. HPCA 2008: 191-202
219EEJason Cong, Karthik Gururaj, Guoling Han, Adam Kaplan, Mishali Naik, Glenn Reinman: MC-Sim: an efficient simulation tool for MPSoC designs. ICCAD 2008: 364-371
218EEAmit Agarwal, Jason Cong, Brian Tagiku: Fault tolerant placement and defect reconfiguration for nano-FPGAs. ICCAD 2008: 714-721
217EEJason Cong, John Lee, Lieven Vandenberghe: Robust gate sizing via mean excess delay minimization. ISPD 2008: 10-14
216EEJason Cong, Guojie Luo: Highly efficient gradient computation for density-constrained analytical placement methods. ISPD 2008: 39-46
215EEM.-C. Frank Chang, Eran Socher, Sai-Wang Tam, Jason Cong, Glenn Reinman: RF interconnects for communications on-chip. ISPD 2008: 78-83
214EEM.-C. Frank Chang, Jason Cong, Adam Kaplan, Chunyue Liu, Mishali Naik, Jagannath Premkumar, Glenn Reinman, Eran Socher, Sai-Wang Tam: Power reduction of CMP communication networks via RF-interconnects. MICRO 2008: 376-387
213EEJason Cong: A new generation of C-base synthesis tool and domain-specific computing. SoCC 2008: 386
212EEJason Cong, Yuzheng Ding: FPGA Technology Mapping. Encyclopedia of Algorithms 2008
211EEJason Cong, Guojie Luo, E. Radke: Highly Efficient Gradient Computation for Density-Constrained Analytical Placement. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2133-2144 (2008)
210EEJason Cong, Min Xie: A Robust Mixed-Size Legalization and Detailed Placement Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1349-1362 (2008)
209EEYuan Xie, Jason Cong, Paul Franzon: Editorial: Special issue on 3D integrated circuits and microarchitectures. JETC 4(4): (2008)
208EEYuchun Ma, Yongxiang Liu, Eren Kursun, Glenn Reinman, Jason Cong: Investigating the effects of fine-grain three-dimensional integration on microarchitecture design. JETC 4(4): (2008)
2007
207EEDeming Chen, Jason Cong, Yiping Fan, Zhiru Zhang: High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs. ASP-DAC 2007: 529-534
206EEJason Cong, Guojie Luo, Jie Wei, Yan Zhang: Thermal-Aware 3D IC Placement Via Transformation. ASP-DAC 2007: 780-785
205EEYuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou: Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. ASP-DAC 2007: 920-925
204EEJason Cong, Kirill Minkovich: Improved SAT-based Boolean matching using implicants for LUT-based FPGAs. FPGA 2007: 139-147
203EEJason Cong, Guoling Han, Wei Jiang: Synthesis of an application-specific soft multiprocessor system. FPGA 2007: 99-107
202EEYongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinman, Jason Cong: Fine grain 3D integration for microarchitecture design through cube packing exploration. ICCD 2007: 259-266
201EEJason Cong, Guoling Han, Ashok Jagannathan, Glenn Reinman, Krzysztof Rutkowski: Accelerating Sequential Applications on CMPs Using Core Spilling. IEEE Trans. Parallel Distrib. Syst. 18(8): 1094-1107 (2007)
200EEJason Cong, Kirill Minkovich: Optimality Study of Logic Synthesis for LUT-Based FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 230-239 (2007)
199EEChen Li, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden: Routability-Driven Placement and White Space Allocation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 858-871 (2007)
2006
198EEJason Cong, Min Xie: A robust detailed placement for mixed-size IC designs. ASP-DAC 2006: 188-194
197EEJason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang: An automated design flow for 3D microarchitecture evaluation. ASP-DAC 2006: 384-389
196EEJason Cong, Zhiru Zhang: An efficient and versatile scheduling algorithm based on SDC formulation. DAC 2006: 433-438
195EEJoey Y. Lin, Deming Chen, Jason Cong: Optimal simultaneous mapping and clustering for FPGA delay optimization. DAC 2006: 472-477
194EEDeming Chen, Jason Cong, Yiping Fan, Junjuan Xu: Optimality study of resource binding with multi-Vdds. DAC 2006: 580-585
193EEJason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang: Behavior and communication co-optimization for systems with sequential communication media. DAC 2006: 675-678
192EEJason Cong, Kirill Minkovich: Optimality study of logic synthesis for LUT-based FPGAs. FPGA 2006: 33-40
191EEJason Cong, Yiping Fan, Wei Jiang: Platform-based resource binding using a distributed register-file microarchitecture. ICCAD 2006: 709-715
190EETony F. Chan, Jason Cong, Joseph R. Shinnerl, Kenton Sze, Min Xie: mPL6: enhanced multilevel mixed-size placement. ISPD 2006: 212-214
189EEDeming Chen, Jason Cong, Junjuan Xu: Optimal simultaneous module and multivoltage assignment for low power. ACM Trans. Design Autom. Electr. Syst. 11(2): 362-386 (2006)
188EEGang Chen, Jason Cong: Simultaneous placement with clustering and duplication. ACM Trans. Design Autom. Electr. Syst. 11(3): 740-772 (2006)
187EEDeming Chen, Jason Cong, Peichen Pan: FPGA Design Automation: A Survey. Foundations and Trends in Electronic Design Automation 1(3): (2006)
186EEJason Cong, Guoling Han, Zhiru Zhang: Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors. IEEE Trans. VLSI Syst. 14(9): 986-997 (2006)
185EEDarko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak, Jason Cong: Protecting Combinational Logic Synthesis Solutions. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2687-2696 (2006)
184EEJason Cong, Michail Romesis, Joseph R. Shinnerl: Fast floorplanning by look-ahead enabled recursive bipartitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1719-1732 (2006)
2005
183EEJason Cong, Tony Ma, Ivo Bolsens, Phil Moorby, Jan M. Rabaey, John Sanguinetti, Kazutoshi Wakabayashi, Yoshi Watanabe: Are we ready for system-level synthesis? ASP-DAC 2005
182EEJason Cong, Michail Romesis, Joseph R. Shinnerl: Fast floorplanning by look-ahead enabled recursive bipartitioning. ASP-DAC 2005: 1119-1122
181EEJason Cong, Yan Zhang: Thermal-driven multilevel routing for 3-D ICs. ASP-DAC 2005: 121-126
180EEAshok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong: Microarchitecture evaluation with floorplanning and interconnect pipelining. ASP-DAC 2005: 8-15
179EEDeming Chen, Jason Cong, Junjuan Xu: Optimal module and voltage assignment for low-power. ASP-DAC 2005: 850-855
178EEJason Cong, Yiping Fan, Guoling Han, Yizhou Lin, Junjuan Xu, Zhiru Zhang, Xu Cheng: Bitwidth-aware scheduling and binding in high-level synthesis. ASP-DAC 2005: 856-861
177EEGang Chen, Jason Cong: Simultaneous timing-driven placement and duplication. FPGA 2005: 51-59
176EEJason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang: Instruction set extension with shadow registers for configurable processors. FPGA 2005: 99-106
175 Jason Cong, Michail Romesis, Joseph R. Shinnerl: Robust mixed-size placement under tight white-space constraints. ICCAD 2005: 165-172
174 Jason Cong, Guoling Han, Zhiru Zhang: Architecture and compilation for data bandwidth improvement in configurable embedded processors. ICCAD 2005: 263-270
173 Jason Cong, Yan Zhang: Thermal via planning for 3-D ICs. ICCAD 2005: 745-752
172EEJunjuan Xu, Jason Cong, Xu Cheng: Lower-bound estimation for multi-bitwidth scheduling. ISCAS (1) 2005: 696-699
171EEJason Cong, Ashok Jagannathan, Glenn Reinman, Yuval Tamir: Understanding the energy efficiency of SMT and CMP with multiclustering. ISLPED 2005: 48-53
170EETony F. Chan, Jason Cong, Kenton Sze: Multilevel generalized force-directed method for circuit placement. ISPD 2005: 185-192
169EETony F. Chan, Jason Cong, Michail Romesis, Joseph R. Shinnerl, Kenton Sze, Min Xie: mPL6: a robust multilevel mixed-size placement engine. ISPD 2005: 227-229
168EEJason Cong, Hui Huang, Xin Yuan: Technology mapping and architecture evalution for k/m-macrocell-based FPGAs. ACM Trans. Design Autom. Electr. Syst. 10(1): 3-23 (2005)
167EEJason Cong, Joseph R. Shinnerl, Min Xie, Tim Kong, Xin Yuan: Large-scale circuit placement. ACM Trans. Design Autom. Electr. Syst. 10(2): 389-430 (2005)
166EEFei Li, Yizhou Lin, Lei He, Deming Chen, Jason Cong: Power modeling and characteristics of field programmable gate arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1712-1724 (2005)
165EEJason Cong, Jie Fang, Min Xie, Yan Zhang: MARS-a multilevel full-chip gridless routing system. IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 382-394 (2005)
2004
164EEDeming Chen, Jason Cong: Register binding and port assignment for multiplexer optimization. ASP-DAC 2004: 68-73
163EENitin Deo, Behrooz Zahiri, Ivo Bolsens, Jason Cong, Bhusan Gupta, Philip Lopresti, Christopher B. Reynolds, Chris Rowen, Ray Simar: What happened to ASIC?: Go (recon)figure? DAC 2004: 185
162EEJason Cong, Yiping Fan, Zhiru Zhang: Architecture-level synthesis for automatic interconnect pipelining. DAC 2004: 602-607
161EEDeming Chen, Jason Cong, Fei Li, Lei He: Low-power technology mapping for FPGA architectures with dual supply voltages. FPGA 2004: 109-117
160EEJason Cong, Yiping Fan, Guoling Han, Zhiru Zhang: Application-specific instruction generation for configurable processor architectures. FPGA 2004: 183-189
159EEFei Li, Yan Lin, Lei He, Jason Cong: Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. FPGA 2004: 42-50
158EEGang Chen, Jason Cong: Simultaneous Timing Driven Clustering and Placement for FPGAs. FPL 2004: 158-167
157EEJason Cong, Jie Wei, Yan Zhang: A thermal-driven floorplanning algorithm for 3D ICs. ICCAD 2004: 306-313
156EEChen Li, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden: Routability-driven placement and white space allocation. ICCAD 2004: 394-401
155EEDeming Chen, Jason Cong: DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs. ICCAD 2004: 752-759
154EEDeming Chen, Jason Cong: Delay optimal low-power circuit clustering for FPGAs with dual supply voltages. ISLPED 2004: 70-73
153EEJason Cong, Gabriele Nataneli, Michail Romesis, Joseph R. Shinnerl: An area-optimality study of floorplanning. ISPD 2004: 78-83
152EEJason Cong, Sung Kyu Lim: Retiming-based timing analysis with an application to mincut-based global placement. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1684-1692 (2004)
151EEJason Cong, Sung Kyu Lim: Edge separability-based circuit clustering with application to multilevel circuit partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 346-357 (2004)
150EEChin-Chih Chang, Jason Cong, Michail Romesis, Min Xie: Optimality and scalability study of existing placement algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 537-549 (2004)
149EEJason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang: Architecture and synthesis for on-chip multicycle communication. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 550-564 (2004)
2003
148EEJason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang: Architecture and synthesis for multi-cycle on-chip communication. CODES+ISSS 2003: 77-78
147EEJason Cong, Xin Yuan: Multilevel global placement with retiming. DAC 2003: 208-213
146EEJason Cong, Ashok Jagannathan, Glenn Reinman, Michail Romesis: Microarchitecture evaluation with physical planning. DAC 2003: 32-35
145EEFei Li, Deming Chen, Lei He, Jason Cong: Architecture evaluation for power-efficient FPGAs. FPGA 2003: 175-184
144EETony F. Chan, Jason Cong, Tim Kong, Joseph R. Shinnerl, Kenton Sze: An Enhanced Multilevel Algorithm for Circuit Placement. ICCAD 2003: 299-306
143EEJason Cong, Michail Romesis, Min Xie: Optimality and Stability Study of Timing-Driven Placement Algorithms. ICCAD 2003: 472-479
142EEZhiru Zhang, Yiping Fan, Miodrag Potkonjak, Jason Cong: Gradual Relaxation Techniques with Applications to Behavioral Synthesis. ICCAD 2003: 529-535
141EEJason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang: Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication. ICCAD 2003: 536-543
140EEJason Cong, Tim Kong, Joseph R. Shinnerl, Min Xie, Xin Yuan: Large-Scale Circuit Placement: Gap and Promise. ICCAD 2003: 883-890
139EEDeming Chen, Jason Cong, Yiping Fan: Low-power high-level synthesis for FPGA architectures. ISLPED 2003: 134-139
138EEJason Cong, Yiping Fan, Xun Yang, Zhiru Zhang: Architecture and synthesis for multi-cycle communication. ISPD 2003: 190-196
137EEJason Cong, Michail Romesis, Min Xie: Optimality, scalability and stability study of partitioning and placement algorithms. ISPD 2003: 88-94
136EEDeming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang: Performance-driven mapping for CPLD architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1424-1431 (2003)
135EEChin-Chih Chang, Jason Cong, David Zhigang Pan, Xin Yuan: Multilevel global placement with congestion control. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 395-409 (2003)
2002
134EEJason Cong, Yizhou Lin, Wangning Long: SPFD-based global rewiring. FPGA 2002: 77-84
133EEJason Cong, Min Xie, Yan Zhang: An enhanced multilevel routing system. ICCAD 2002: 51-58
132EEJason Cong, Joey Y. Lin, Wangning Long: A new enhanced SPFD rewiring algorithm. ICCAD 2002: 672-678
131EEJason Cong, Chang Wu: Global clustering-based performance-driven circuit partitioning. ISPD 2002: 149-154
130EEJason Cong: Timing closure based on physical hierarchy. ISPD 2002: 170-174
129EEChin-Chih Chang, Jason Cong, David Zhigang Pan: Physical hierarchy generation with routing congestion control. ISPD 2002: 36-41
128 Jason Cong, Joey Y. Lin, Wangning Long: Enhanced SPFD Rewiring on Improving Rewiring Ability. IWLS 2002: 91-96
127EEJason Cong, David Zhigang Pan: Wire width planning for interconnect performance optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 21(3): 319-329 (2002)
126EETaku Uchino, Jason Cong: An interconnect energy model considering coupling effects. IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 763-776 (2002)
2001
125EEJason Cong, David Zhigang Pan, Prasanna V. Srinivas: Improved crosstalk modeling for noise constrained interconnect optimization. ASP-DAC 2001: 373-378
124EEJason Cong, Michail Romesis: Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping. DAC 2001: 389-394
123EETaku Uchino, Jason Cong: An Interconnect Energy Model Considering Coupling Effects. DAC 2001: 555-558
122EEDeming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang: Performance-driven mapping for CPLD architectures. FPGA 2001: 39-47
121EEGang Chen, Jason Cong: Simultaneous logic decomposition with technology mapping in FPGA designs. FPGA 2001: 48-55
120EEJason Cong, Jie Fang, Yan Zhang VI: Multilevel Approach to Full-Chip Gridless Routing. ICCAD 2001: 396-403
119EEJason Cong, Tianming Kong, Z. D. Pan: Buffer block planning for interconnect planning and prediction. IEEE Trans. VLSI Syst. 9(6): 929-937 (2001)
118EEJason Cong, Cheng-Kok Koh, Patrick H. Madden: Interconnect layout optimization under higher order RLC model forMCM designs. IEEE Trans. on CAD of Integrated Circuits and Systems 20(12): 1455-1463 (2001)
117EEChin-Chih Chang, Jason Cong: Pseudopin assignment with crosstalk noise control. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 598-611 (2001)
116EEJason Cong, Jie Fang, Kei-Yong Khoo: DUNE-a multilayer gridless routing system. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 633-647 (2001)
115EEJason Cong, David Zhigang Pan: Interconnect performance estimation models for design planning. IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 739-752 (2001)
114EEJason Cong, Yean-Yow Hwang: Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping. IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1077-1090 (2001)
113EEJason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan: Interconnect sizing and spacing with consideration of couplingcapacitance. IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1164-1169 (2001)
2000
112EEJason Cong, Songjie Xu: Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs. ASP-DAC 2000: 157-162
111EEJason Cong, Tianming Kong, Faming Liang, Jun S. Liu, Wing Hung Wong, Dongmin Xu: Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application. ASP-DAC 2000: 277-282
110EEJason Cong, Sung Kyu Lim: Edge separability based circuit clustering with application to circuit partitioning. ASP-DAC 2000: 429-434
109EEJason Cong, Sung Kyu Lim: Performance driven multiway partitioning. ASP-DAC 2000: 441-446
108EEMaogang Wang, Sung Lim, Jason Cong, Majid Sarrafzadeh: Multi-way partitioning using bi-partition heuristics. ASP-DAC 2000: 667
107EEJason Cong, Sung Kyu Lim, Chang Wu: Performance driven multi-level and multiway partitioning with retiming. DAC 2000: 274-279
106EEJason Cong, Hui Huang: Depth optimal incremental mapping for field programmable gate arrays. DAC 2000: 290-293
105EEJason Cong, Xin Yuan: Routing tree construction under fixed buffer locations. DAC 2000: 379-384
104EEJason Cong, Hui Huang, Xin Yuan: Technology mapping for k/m-macrocell based FPGAs. FPGA 2000: 51-59
103EEJason Cong, Kenneth Yan: Synthesis for FPGAs with embedded memory blocks. FPGA 2000: 75-82
102 Tony F. Chan, Jason Cong, Tianming Kong, Joseph R. Shinnerl: Multilevel Optimization for Large-Scale Circuit Placement. ICCAD 2000: 171-176
101 Jason Cong, Sung Kyu Lim: Physical Planning with Retiming. ICCAD 2000: 2-7
100 Olivier Coudert, Jason Cong, Sharad Malik, Majid Sarrafzadeh: Incremental CAD. ICCAD 2000: 236-243
99EEJason Cong, Jie Fang, Kei-Yong Khoo: DUNE: a multi-layer gridless routing system with wire planning. ISPD 2000: 12-18
98EEChin-Chih Chang, Jason Cong: Pseudo pin assignment with crosstalk noise control. ISPD 2000: 41-47
97EEJason Cong, Majid Sarrafzadeh: Incremental physical design. ISPD 2000: 84-92
96EEJason Cong, Yean-Yow Hwang: Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs. ACM Trans. Design Autom. Electr. Syst. 5(2): 193-225 (2000)
95EEJason Cong, Songjie Xu: Performance-driven technology mapping for heterogeneous FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1268-1281 (2000)
94EEJason Cong, Jie Fang, Kei-Yong Khoo: Via design rule consideration in multilayer maze routing algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 215-223 (2000)
1999
93 Farid N. Najm, Jason Cong, David Blaauw: Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, San Diego, California, USA, August 16-17, 1999 ACM 1999
92EEJason Cong, Tianming Kong, Dongmin Xu, Faming Liang, Jun S. Liu, Wing Hung Wong: Relaxed Simulated Tempering for VLSI Floorplan Designs. ASP-DAC 1999: 13-16
91EEJason Cong, David Zhigang Pan: Interconnect Delay Estimation Models for Synthesis and Design Planning. ASP-DAC 1999: 97-100
90EEJason Cong, Yean-Yow Hwang, Songjie Xu: Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections. DAC 1999: 373-378
89EEJason Cong, Honching Li, Chang Wu: Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization. DAC 1999: 460-465
88EEJason Cong, David Zhigang Pan: Interconnect Estimation and Dlanning for Deep Submicron Designs. DAC 1999: 507-510
87EEJason Cong, Chang Wu, Yuzheng Ding: Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution. FPGA 1999: 29-35
86EEJason Cong, Jie Fang, Kei-Yong Khoo: An implicit connection graph maze routing algorithm for ECO routing. ICCAD 1999: 163-167
85EEJason Cong, Tianming Kong, David Zhigang Pan: Buffer block planning for interconnect-driven floorplanning. ICCAD 1999: 358-363
84EEJason Cong, Jie Fang, Kei-Yong Khoo: VIA design rule consideration in multi-layer maze routing algorithms. ISPD 1999: 214-220
83EEJason Cong, Chang Wu: Optimal FPGA mapping and retiming with efficient initial state computation. IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1595-1607 (1999)
82EEJason Cong, Lei He: Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 406-420 (1999)
81EEChin-Chih Chang, Jason Cong: An efficient approach to multilayer layer assignment with anapplication to via minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 18(5): 608-620 (1999)
1998
80EEJason Cong, Chang Wu: Optimal FPGA Mapping and Retiming with Efficient Initial State Computation. DAC 1998: 330-335
79EEJason Cong, Patrick H. Madden: Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs. DAC 1998: 356-361
78EEJason Cong, Songjie Xu: Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs. DAC 1998: 704-707
77EEJason Cong, Songjie Xu: Technology Mapping for FPGAs with Embedded Memory Blocks. FPGA 1998: 179-188
76EEJason Cong, Yean-Yow Hwang: Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation. FPGA 1998: 27-34
75EEDarko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak, Jason Cong: Intellectual property protection by watermarking combinational logic synthesis solutions. ICCAD 1998: 194-198
74EEJason Cong, Songjie Xu: Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources. ICCAD 1998: 40-44
73EERobert C. Aitken, Jason Cong, Randy Harr, Kenneth L. Shepard, Wayne Wolf: How will CAD handle billion-transistor systems? (panel). ICCAD 1998: 5
72EEJason Cong, Sung Kyu Lim: Multiway partitioning with pairwise movement. ICCAD 1998: 512-516
71EEJason Cong, Lei He: An efficient technique for device and interconnect optimization in deep submicron designs. ISPD 1998: 45-51
70EEJason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao: Bounded-skew clock and Steiner routing. ACM Trans. Design Autom. Electr. Syst. 3(3): 341-388 (1998)
69EEJason Cong, Andrew B. Kahng, Kwok-Shing Leung: Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. IEEE Trans. on CAD of Integrated Circuits and Systems 17(1): 24-39 (1998)
68EEJason Cong, Chang Wu: An efficient algorithm for performance-optimal FPGA technology mapping with retiming. IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 738-748 (1998)
1997
67EEChin-Chih Chang, Jason Cong: An Efficient Approach to Multi-Layer Layer Assignment with Application to Via Minimization. DAC 1997: 600-603
66EEJason Cong, Lei He, Andrew B. Kahng, David Noice, Nagesh Shirali, Steve H.-C. Yen: Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology. DAC 1997: 627-632
65EEJason Cong, Chang Wu: FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits. DAC 1997: 644-649
64EEJason Cong, John Peck: On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor. FCCM 1997: 246-248
63EEJason Cong, Yean-Yow Hwang: Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping. FPGA 1997: 35-42
62EEJason Cong, Honching Peter Li, Sung Kyu Lim, Toshiyuki Shibuya, Dongmin Xu: Large scale circuit partitioning with loose/stable net removal and signal flow based clustering. ICCAD 1997: 441-446
61EEJason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo: Interconnect design for deep submicron ICs. ICCAD 1997: 478-485
60EEJason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan: Global interconnect sizing and spacing with consideration of coupling capacitance. ICCAD 1997: 628-633
59EEJason Cong, Cheng-Kok Koh: Interconnect layout optimization under higher-order RLC model. ICCAD 1997: 713-720
58EEJason Cong, Patrick H. Madden: Performance driven global routing for standard cell design. ISPD 1997: 73-80
57EEJason Cong, Andrew B. Kahng, Kwok-Shing Leung: Efficient heuristics for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. ISPD 1997: 88-95
56EEJason Cong, Patrick H. Madden: Performance-driven routing with multiple sources. IEEE Trans. on CAD of Integrated Circuits and Systems 16(4): 410-419 (1997)
1996
55EEJason Cong, Yean-Yow Hwang: Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design. DAC 1996: 726-729
54EEJason Cong, John Peck, Yuzheng Ding: RASP: A General Logic Synthesis System for SRAM-Based FPGAs. FPGA 1996: 137-143
53EEJason Cong, Lei He: An efficient approach to simultaneous transistor and interconnect sizing. ICCAD 1996: 181-186
52EETakumi Okamoto, Jason Cong: Buffered Steiner tree construction with wire sizing for interconnect layout optimization. ICCAD 1996: 44-49
51EEJason Cong, Chang Wu: An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA Desig. ICCD 1996: 572-578
50EEJason Cong, Cheng-Kok Koh, Kwok-Shing Leung: Simultaneous buffer and wire sizing for performance and power optimization. ISLPED 1996: 271-276
49EEJason Cong, Yuzheng Ding: Combinational logic synthesis for LUT based field programmable gate arrays. ACM Trans. Design Autom. Electr. Syst. 1(2): 145-204 (1996)
48EEJason Cong, Lei He: Optimal wiresizing for interconnects with multiple sources. ACM Trans. Design Autom. Electr. Syst. 1(4): 478-511 (1996)
47EEJason Cong, Wilburt Labio, Narayanan Shivakumar: Multiway VLSI circuit partitioning based on dual net representation. IEEE Trans. on CAD of Integrated Circuits and Systems 15(4): 396-409 (1996)
46EEJason Cong, Lei He, Cheng-Kok Koh, Patrick H. Madden: Performance optimization of VLSI interconnect layout. Integration 21(1-2): 1-94 (1996)
1995
45EEJason Cong, Dongmin Xu: Exploitation signal flow and logic dependency in standard cell placement. ASP-DAC 1995
44EEJason Cong, Yean-Yow Hwang: Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping. FPGA 1995: 68-74
43EEJason Cong, Yuzheng Ding: On Nominal Delay Minimization in LUT-based FPGA Technology Mapping. FPGA 1995: 82-88
42EEJason Cong, Lei He: Optimal wiresizing for interconnects with multiple sources. ICCAD 1995: 568-574
41EEJason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao: Bounded-skew clock and Steiner routing under Elmore delay. ICCAD 1995: 66-71
40 Jason Cong, Patrick H. Madden: Performance Driven Routing with Mulitiple Sources. ISCAS 1995: 203-206
39 Jason Cong, Cheng-Kok Koh: Minimum-Cost Bounded-Skew Clock Routing. ISCAS 1995: 215-218
38EEKei-Yong Khoo, Jason Cong: An efficient multilayer MCM router based on four-via routing. IEEE Trans. on CAD of Integrated Circuits and Systems 14(10): 1277-1290 (1995)
37EEJason Cong, Kwok-Shing Leung: Optimal wiresizing under Elmore delay model. IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 321-336 (1995)
1994
36EEJason Cong, Zheng Li, Rajive Bagrodia: Acyclic Multi-Way Partitioning of Boolean Networks. DAC 1994: 670-675
35EEJason Cong, Cheng-Kok Koh: Simultaneous driver and wire sizing for performance and power optimization. ICCAD 1994: 206-212
34EEJason Cong, Wilburt Labio, Narayanan Shivakumar: Multi-way VLSI circuit partitioning based on dual net representation. ICCAD 1994: 56-62
33EERajive Bagrodia, Zheng Li, Vikas Jha, Yuan Chen, Jason Cong: Parallel logic level simulation of VLSI circuits. Winter Simulation Conference 1994: 1354-1361
32EEJason Cong, Yuzheng Ding, Tong Gao, Kuang-Chien Chen: LUT-based FPGA technology mapping under arbitrary net-delay models. Computers & Graphics 18(4): 507-516 (1994)
31EEJason Cong, Yuzheng Ding: On area/depth trade-off in LUT-based FPGA technology mapping. IEEE Trans. VLSI Syst. 2(2): 137-148 (1994)
30EEJason Cong, Cheng-Kok Koh: Simultaneous driver and wire sizing for performance and power optimization. IEEE Trans. VLSI Syst. 2(4): 408-425 (1994)
29EEJason Cong, Yuzheng Ding: FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. IEEE Trans. on CAD of Integrated Circuits and Systems 13(1): 1-12 (1994)
1993
28EEJason Cong, Yuzheng Ding: On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping. DAC 1993: 213-218
27EEKei-Yong Khoo, Jason Cong: An Efficient Multilayer MCM Router Based on Four-Via Routing. DAC 1993: 590-595
26EEJason Cong, Kwok-Shing Leung, Dian Zhou: Performance-Driven Interconnect Design Based on Distributed RC Delay Model. DAC 1993: 606-611
25EEJason Cong, M'Lissa Smith: A Parallel Bottom-Up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design. DAC 1993: 755-760
24EEJason Cong, Yuzheng Ding: Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs. ICCAD 1993: 110-114
23EEJason Cong, Kwok-Shing Leung: Optimal wiresizing under the distributed Elmore delay model. ICCAD 1993: 634-639
22 Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh: Minimum Density Interconneciton Trees. ISCAS 1993: 1865-1868
21 Dian Zhou, S. Su, F. Tsui, D. S. Gao, Jason Cong: A Two-pole Circuit Model for VLSI High-speed Interconnection. ISCAS 1993: 2129-2132
20 Jason Cong, Moazzem Hossain, Naveed A. Sherwani: A Provably Good Algorithm for k-Layer Topological Planar Routing Problems. VLSI Design 1993: 113
19EEJason Cong, Moazzem Hossain, Naveed A. Sherwani: A provably good multilayer topological planar routing algorithm in IC layout designs. IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 70-78 (1993)
18EEJason Cong, Bryan Preas, C. L. Liu: Physical models and efficient algorithms for over-the-cell routing in standard cell design. IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 723-734 (1993)
17EEJason Cong, Andrew B. Kahng, Gabriel Robins: Matching-based methods for high-performance clock routing. IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1157-1169 (1993)
1992
16EEJason Cong, Lars W. Hagen, Andrew B. Kahng: Net Partitions Yield Better Module Partitions. DAC 1992: 47-52
15EEJason Cong, Yuzheng Ding: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. ICCAD 1992: 48-53
14 Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen: An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization. ICCD 1992: 154-158
13EEKuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar: DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. IEEE Design & Test of Computers 9(3): 7-20 (1992)
12EEJason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, Chak-Kuen Wong: Provably good performance-driven global routing. IEEE Trans. on CAD of Integrated Circuits and Systems 11(6): 739-752 (1992)
1991
11EEAndrew B. Kahng, Jason Cong, Gabriel Robins: High-Performance Clock Routing Based on Recursive Geometric Aatching. DAC 1991: 322-327
10 Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, C. K. Wong: Performance-Driven Global Routing for Cell Based ICs. ICCD 1991: 170-173
9 Jason Cong, Kei-Yong Khoo: A Provable Near-Optimal Algorithm for the Channel Pin Assignment Problem. ICCD 1991: 319-322
8EEJason Cong: Pin assignment with global routing for general cell designs. IEEE Trans. on CAD of Integrated Circuits and Systems 10(11): 1401-1412 (1991)
7EEKhe-Sing The, Martin D. F. Wong, Jason Cong: A layout modification approach to via minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 10(4): 536-541 (1991)
6EEJason Cong, C. L. Liu: On the k-layer planar subset and topological via minimization problems. IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 972-981 (1991)
1990
5EEJason Cong, Bryan Preas, C. L. Liu: General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design. DAC 1990: 709-715
4EEJason Cong, C. L. Liu: On the k-layer planar subset and via minimization problems. EURO-DAC 1990: 459-463
3EEJason Cong, C. L. Liu: Over-the-cell channel routing. IEEE Trans. on CAD of Integrated Circuits and Systems 9(4): 408-418 (1990)
1989
2EEKhe-Sing The, D. F. Wong, Jason Cong: VIA Minimization by Layout Modification. DAC 1989: 799-802
1988
1EEJason Cong, Martin D. F. Wong, C. L. Liu: A new approach to three- or four-layer channel routing. IEEE Trans. on CAD of Integrated Circuits and Systems 7(10): 1094-1104 (1988)

Coauthor Index

1Amit Agarwal [218]
2Robert C. Aitken (Rob Aitken) [73]
3Charles J. Alpert [22]
4Rajive Bagrodia [33] [36]
5David Blaauw (David T. Blaauw) [93]
6Ivo Bolsens [163] [183]
7Jeff Burns [234]
8Tony F. Chan [102] [144] [169] [170] [190]
9Chin-Chih Chang [67] [81] [98] [117] [129] [135] [150]
10M. Frank Chang [220]
11Mau-Chung Frank Chang (M.-C. Frank Chang) [214] [215]
12Shih-Chieh Chang [227]
13Deming Chen [122] [136] [139] [145] [154] [155] [161] [164] [166] [179] [187] [189] [194] [195] [207] [229]
14Gang Chen [121] [158] [177] [188]
15Kuang-Chien Chen [13] [14] [32]
16Yuan Chen [33]
17Xu Cheng [172] [178]
18Olivier Coudert [100]
19Nitin Deo [163]
20Yuzheng Ding [13] [14] [15] [24] [28] [29] [31] [32] [43] [49] [54] [87] [212]
21Sheqin Dong [205] [226]
22Milos D. Ercegovac [122] [136]
23Yiping Fan [138] [139] [141] [142] [148] [149] [160] [162] [176] [178] [191] [193] [194] [207] [228]
24Jie Fang [84] [86] [94] [99] [116] [120] [165]
25Paul Franzon [209]
26D. S. Gao [21]
27Tong Gao [32]
28Moshe Gavrielov [234]
29Bhusan Gupta [163]
30Puneet Gupta [237]
31Karthik Gururaj [219] [229] [230] [231] [232]
32Lars W. Hagen [16]
33Guoling Han [141] [148] [149] [160] [174] [176] [178] [186] [193] [201] [203] [219] [231]
34Eshel Haritan [233]
35Randy Harr [73]
36Lei He [42] [46] [48] [53] [60] [61] [66] [71] [82] [113] [145] [159] [161] [166]
37Xianlong Hong [205] [226]
38Moazzem Hossain [19] [20]
39Cheng-Tao Hsieh [227]
40Hui Huang [104] [106] [168]
41Zhijun Huang [122] [136]
42Yean-Yow Hwang [44] [55] [63] [75] [76] [90] [96] [114] [185]
43Wen-mei W. Hwu [229]
44Ashok Jagannathan [146] [171] [176] [180] [197] [201]
45Vikas Jha [33]
46Wei Jiang [191] [193] [203] [223] [225]
47William H. Joyner [234]
48Andrew B. Kahng [10] [11] [12] [13] [14] [16] [17] [22] [41] [57] [66] [69] [70]
49Adam Kaplan [214] [219] [220]
50Kei-Yong Khoo [9] [27] [38] [61] [84] [86] [94] [99] [116]
51Darko Kirovski [75] [185]
52Tim Kogel [233]
53Cheng-Kok Koh [30] [35] [39] [41] [46] [50] [59] [60] [61] [70] [113] [118] [156] [199]
54Tianming Kong [85] [92] [102] [111] [119]
55Tim Kong [140] [144] [167]
56Kris Konigsfeld [180]
57Stan Krolikoski [233]
58Eren Kursun [202] [208]
59Wilburt Labio [34] [47]
60John Lee [217] [237]
61Kwok-Shing Leung [23] [26] [37] [50] [57] [69]
62Fei Li [145] [159] [161] [166]
63Honching Li [89]
64Honching Peter Li [62]
65Xin Li [226]
66Zheng Li [33] [36]
67Zhuoyuan Li [205]
68Chen Li [156] [199]
69Faming Liang [92] [111]
70Sung Lim [108]
71Sung Kyu Lim [62] [72] [101] [107] [109] [110] [151] [152]
72Joey Y. Lin [128] [132] [195]
73Yan Lin [159]
74Yizhou Lin [134] [166] [178]
75Albert Liu [235]
76Bin Liu [230] [235]
77C. L. Liu (Chung Laung (Dave) Liu) [1] [3] [4] [5] [6] [18]
78Chunyue Liu [214] [230]
79Jun S. Liu [92] [111]
80Yongxiang Liu [202] [208]
81Wangning Long [128] [132] [134]
82Philip Lopresti [163]
83Guojie Luo [206] [211] [216] [236]
84Tony Ma [183]
85Yuchun Ma [197] [202] [205] [208] [226]
86Patrick H. Madden [40] [46] [56] [58] [79] [118] [156] [199]
87Sharad Malik [100]
88Bradley D. McCredie [233]
89Dan Milliron [180]
90Kirill Minkovich [192] [200] [204] [222]
91Mosur Mohan [180]
92Phil Moorby [183]
93N. S. Nagaraj [234]
94Mishali Naik [214] [219] [220]
95Farid N. Najm [93]
96Gabriele Nataneli [153]
97David Noice [66]
98Takumi Okamoto [52]
99David Z. Pan (David Zhigang Pan) [60] [61] [85] [88] [91] [113] [115] [125] [127] [129] [135]
100Peichen Pan [187]
101Z. D. Pan [119]
102Alexandros Papakonstantinou [229]
103John Peck [54] [64]
104Miodrag Potkonjak [75] [142] [185] [225]
105Bryan Preas [5] [18]
106Jagannath Premkumar [214]
107Ruchir Puri [233] [234]
108Jan M. Rabaey [183]
109E. Radke [211]
110Riko Radojcic [234]
111Glenn Reinman [146] [171] [176] [180] [197] [201] [202] [205] [208] [214] [215] [219] [220]
112Christopher B. Reynolds [163]
113Peter Rickert [234]
114Gabriel Robins [10] [11] [12] [17] [22]
115Michail Romesis [124] [137] [143] [146] [150] [153] [169] [175] [180] [182] [184]
116Chris Rowen (Christopher Rowen) [163]
117Krzysztof Rutkowski [201]
118John Sanguinetti [183]
119Majid Sarrafzadeh [10] [12] [22] [97] [100] [108]
120John Shen [233]
121Kenneth L. Shepard [73]
122Naveed A. Sherwani [19] [20]
123Toshiyuki Shibuya [62]
124Joseph R. Shinnerl [102] [140] [144] [153] [167] [169] [175] [182] [184] [190]
125Nagesh Shirali [66]
126Narayanan Shivakumar [34] [47]
127Ray Simar [163]
128M'Lissa Smith [25]
129Eran Socher [214] [215] [220]
130Prasanna V. Srinivas [125]
131Hans Stork [234]
132John A. Stratton [229]
133S. Su [21]
134Kenton Sze [144] [169] [170] [190]
135Brian Tagiku [218]
136Andrés Takach [233]
137Sai-Wang Tam [214] [215] [220]
138Yuval Tamir [171]
139Khe-Sing The [2] [7]
140Peter Trajmar [13] [14]
141Chung-Wen Albert Tsao [41] [70]
142F. Tsui [21]
143Taku Uchino [123] [126]
144Yan Zhang VI [120]
145Lieven Vandenberghe [217]
146Kazutoshi Wakabayashi [183]
147Maogang Wang [108]
148Yoshi Watanabe [183]
149Jie Wei [157] [197] [206]
150Wayne Wolf [73]
151Chak-Kuen Wong (C. K. Wong) [10] [12]
152Martin D. F. Wong (D. F. Wong) [1] [2] [7]
153Wing Hung Wong [92] [111]
154Chang Wu [51] [65] [68] [80] [83] [87] [89] [107] [131]
155Min Xie [133] [137] [140] [143] [150] [156] [165] [167] [169] [190] [198] [199] [210]
156Yuan Xie [209]
157Dongmin Xu [45] [62] [92] [111]
158Junjuan Xu [172] [178] [179] [189] [194] [224] [228]
159Songjie Xu [74] [77] [78] [90] [95] [112]
160Kenneth Yan [103]
161Hannah Honghua Yang (Honghua Yang) [180]
162Xun Yang [138] [141] [148] [149]
163Steve H.-C. Yen [66]
164Xin Yuan [104] [105] [135] [140] [147] [167] [168]
165Behrooz Zahiri [163]
166Yan Zhang [133] [157] [165] [173] [181] [197] [206]
167Zhiru Zhang [138] [141] [142] [148] [149] [160] [162] [174] [176] [178] [186] [193] [196] [207] [225] [227] [230]
168Dian Zhou [21] [26]
169Qiang Zhou [205]
170Sheng Zhou [230]
171Yi Zou [221] [230]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)