| 2008 |
|---|
| 214 | EE | Cheng-Tao Hsieh,
Jason Cong,
Zhiru Zhang,
Shih-Chieh Chang:
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA.
ASP-DAC 2008: 10-15 |
| 213 | EE | Xin Li,
Yuchun Ma,
Xianlong Hong,
Sheqin Dong,
Jason Cong:
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs.
ASP-DAC 2008: 209-212 |
| 212 | EE | Wei Jiang,
Zhiru Zhang,
Miodrag Potkonjak,
Jason Cong:
Scheduling with integer time budgeting for low-power optimization.
ASP-DAC 2008: 22-27 |
| 211 | EE | Jason Cong,
Wei Jiang:
Pattern-based behavior synthesis for FPGA resource reduction.
FPGA 2008: 107-116 |
| 210 | EE | Kirill Minkovich,
Jason Cong:
Mapping for better than worst-case delays in LUT-based FPGA designs.
FPGA 2008: 56-64 |
| 209 | EE | Jason Cong,
Yi Zou:
Lithographic aerial image simulation with FPGA-based hardwareacceleration.
FPGA 2008: 67-76 |
| 208 | EE | Jason Cong,
John Lee,
Lieven Vandenberghe:
Robust gate sizing via mean excess delay minimization.
ISPD 2008: 10-14 |
| 207 | EE | Jason Cong,
Guojie Luo:
Highly efficient gradient computation for density-constrained analytical placement methods.
ISPD 2008: 39-46 |
| 206 | EE | M.-C. Frank Chang,
Eran Socher,
Sai-Wang Tam,
Jason Cong,
Glenn Reinman:
RF interconnects for communications on-chip.
ISPD 2008: 78-83 |
| 2007 |
|---|
| 205 | EE | Deming Chen,
Jason Cong,
Yiping Fan,
Zhiru Zhang:
High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs.
ASP-DAC 2007: 529-534 |
| 204 | EE | Jason Cong,
Guojie Luo,
Jie Wei,
Yan Zhang:
Thermal-Aware 3D IC Placement Via Transformation.
ASP-DAC 2007: 780-785 |
| 203 | EE | Yuchun Ma,
Zhuoyuan Li,
Jason Cong,
Xianlong Hong,
Glenn Reinman,
Sheqin Dong,
Qiang Zhou:
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning.
ASP-DAC 2007: 920-925 |
| 202 | EE | Jason Cong,
Kirill Minkovich:
Improved SAT-based Boolean matching using implicants for LUT-based FPGAs.
FPGA 2007: 139-147 |
| 201 | EE | Jason Cong,
Guoling Han,
Wei Jiang:
Synthesis of an application-specific soft multiprocessor system.
FPGA 2007: 99-107 |
| 200 | EE | Jason Cong,
Guoling Han,
Ashok Jagannathan,
Glenn Reinman,
Krzysztof Rutkowski:
Accelerating Sequential Applications on CMPs Using Core Spilling.
IEEE Trans. Parallel Distrib. Syst. 18(8): 1094-1107 (2007) |
| 199 | EE | Jason Cong,
Kirill Minkovich:
Optimality Study of Logic Synthesis for LUT-Based FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 230-239 (2007) |
| 198 | EE | Chen Li,
Min Xie,
Cheng-Kok Koh,
Jason Cong,
Patrick H. Madden:
Routability-Driven Placement and White Space Allocation.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 858-871 (2007) |
| 2006 |
|---|
| 197 | EE | Jason Cong,
Min Xie:
A robust detailed placement for mixed-size IC designs.
ASP-DAC 2006: 188-194 |
| 196 | EE | Jason Cong,
Ashok Jagannathan,
Yuchun Ma,
Glenn Reinman,
Jie Wei,
Yan Zhang:
An automated design flow for 3D microarchitecture evaluation.
ASP-DAC 2006: 384-389 |
| 195 | EE | Jason Cong,
Zhiru Zhang:
An efficient and versatile scheduling algorithm based on SDC formulation.
DAC 2006: 433-438 |
| 194 | EE | Joey Y. Lin,
Deming Chen,
Jason Cong:
Optimal simultaneous mapping and clustering for FPGA delay optimization.
DAC 2006: 472-477 |
| 193 | EE | Deming Chen,
Jason Cong,
Yiping Fan,
Junjuan Xu:
Optimality study of resource binding with multi-Vdds.
DAC 2006: 580-585 |
| 192 | EE | Jason Cong,
Yiping Fan,
Guoling Han,
Wei Jiang,
Zhiru Zhang:
Behavior and communication co-optimization for systems with sequential communication media.
DAC 2006: 675-678 |
| 191 | EE | Jason Cong,
Kirill Minkovich:
Optimality study of logic synthesis for LUT-based FPGAs.
FPGA 2006: 33-40 |
| 190 | EE | Jason Cong,
Yiping Fan,
Wei Jiang:
Platform-based resource binding using a distributed register-file microarchitecture.
ICCAD 2006: 709-715 |
| 189 | EE | Tony F. Chan,
Jason Cong,
Joseph R. Shinnerl,
Kenton Sze,
Min Xie:
mPL6: enhanced multilevel mixed-size placement.
ISPD 2006: 212-214 |
| 188 | EE | Deming Chen,
Jason Cong,
Junjuan Xu:
Optimal simultaneous module and multivoltage assignment for low power.
ACM Trans. Design Autom. Electr. Syst. 11(2): 362-386 (2006) |
| 187 | EE | Gang Chen,
Jason Cong:
Simultaneous placement with clustering and duplication.
ACM Trans. Design Autom. Electr. Syst. 11(3): 740-772 (2006) |
| 186 | EE | Deming Chen,
Jason Cong,
Peichen Pan:
FPGA Design Automation: A Survey.
Foundations and Trends in Electronic Design Automation 1(3): (2006) |
| 185 | EE | Jason Cong,
Guoling Han,
Zhiru Zhang:
Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors.
IEEE Trans. VLSI Syst. 14(9): 986-997 (2006) |
| 184 | EE | Darko Kirovski,
Yean-Yow Hwang,
Miodrag Potkonjak,
Jason Cong:
Protecting Combinational Logic Synthesis Solutions.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2687-2696 (2006) |
| 183 | EE | Jason Cong,
Michail Romesis,
Joseph R. Shinnerl:
Fast floorplanning by look-ahead enabled recursive bipartitioning.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1719-1732 (2006) |
| 2005 |
|---|
| 182 | EE | Jason Cong,
Tony Ma,
Ivo Bolsens,
Phil Moorby,
Jan M. Rabaey,
John Sanguinetti,
Kazutoshi Wakabayashi,
Yoshi Watanabe:
Are we ready for system-level synthesis?
ASP-DAC 2005 |
| 181 | EE | Jason Cong,
Michail Romesis,
Joseph R. Shinnerl:
Fast floorplanning by look-ahead enabled recursive bipartitioning.
ASP-DAC 2005: 1119-1122 |
| 180 | EE | Jason Cong,
Yan Zhang:
Thermal-driven multilevel routing for 3-D ICs.
ASP-DAC 2005: 121-126 |
| 179 | EE | Ashok Jagannathan,
Hannah Honghua Yang,
Kris Konigsfeld,
Dan Milliron,
Mosur Mohan,
Michail Romesis,
Glenn Reinman,
Jason Cong:
Microarchitecture evaluation with floorplanning and interconnect pipelining.
ASP-DAC 2005: 8-15 |
| 178 | EE | Deming Chen,
Jason Cong,
Junjuan Xu:
Optimal module and voltage assignment for low-power.
ASP-DAC 2005: 850-855 |
| 177 | EE | Jason Cong,
Yiping Fan,
Guoling Han,
Yizhou Lin,
Junjuan Xu,
Zhiru Zhang,
Xu Cheng:
Bitwidth-aware scheduling and binding in high-level synthesis.
ASP-DAC 2005: 856-861 |
| 176 | EE | Gang Chen,
Jason Cong:
Simultaneous timing-driven placement and duplication.
FPGA 2005: 51-59 |
| 175 | EE | Jason Cong,
Yiping Fan,
Guoling Han,
Ashok Jagannathan,
Glenn Reinman,
Zhiru Zhang:
Instruction set extension with shadow registers for configurable processors.
FPGA 2005: 99-106 |
| 174 | | Jason Cong,
Michail Romesis,
Joseph R. Shinnerl:
Robust mixed-size placement under tight white-space constraints.
ICCAD 2005: 165-172 |
| 173 | | Jason Cong,
Guoling Han,
Zhiru Zhang:
Architecture and compilation for data bandwidth improvement in configurable embedded processors.
ICCAD 2005: 263-270 |
| 172 | | Jason Cong,
Yan Zhang:
Thermal via planning for 3-D ICs.
ICCAD 2005: 745-752 |
| 171 | EE | Junjuan Xu,
Jason Cong,
Xu Cheng:
Lower-bound estimation for multi-bitwidth scheduling.
ISCAS (1) 2005: 696-699 |
| 170 | EE | Jason Cong,
Ashok Jagannathan,
Glenn Reinman,
Yuval Tamir:
Understanding the energy efficiency of SMT and CMP with multiclustering.
ISLPED 2005: 48-53 |
| 169 | EE | Tony F. Chan,
Jason Cong,
Kenton Sze:
Multilevel generalized force-directed method for circuit placement.
ISPD 2005: 185-192 |
| 168 | EE | Tony F. Chan,
Jason Cong,
Michail Romesis,
Joseph R. Shinnerl,
Kenton Sze,
Min Xie:
mPL6: a robust multilevel mixed-size placement engine.
ISPD 2005: 227-229 |
| 167 | EE | Jason Cong,
Hui Huang,
Xin Yuan:
Technology mapping and architecture evalution for k/m-macrocell-based FPGAs.
ACM Trans. Design Autom. Electr. Syst. 10(1): 3-23 (2005) |
| 166 | EE | Jason Cong,
Joseph R. Shinnerl,
Min Xie,
Tim Kong,
Xin Yuan:
Large-scale circuit placement.
ACM Trans. Design Autom. Electr. Syst. 10(2): 389-430 (2005) |
| 165 | EE | Fei Li,
Yizhou Lin,
Lei He,
Deming Chen,
Jason Cong:
Power modeling and characteristics of field programmable gate arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1712-1724 (2005) |
| 164 | EE | Jason Cong,
Jie Fang,
Min Xie,
Yan Zhang:
MARS-a multilevel full-chip gridless routing system.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 382-394 (2005) |
| 2004 |
|---|
| 163 | EE | Deming Chen,
Jason Cong:
Register binding and port assignment for multiplexer optimization.
ASP-DAC 2004: 68-73 |
| 162 | EE | Nitin Deo,
Behrooz Zahiri,
Ivo Bolsens,
Jason Cong,
Bhusan Gupta,
Philip Lopresti,
Christopher B. Reynolds,
Chris Rowen,
Ray Simar:
What happened to ASIC?: Go (recon)figure?
DAC 2004: 185 |
| 161 | EE | Jason Cong,
Yiping Fan,
Zhiru Zhang:
Architecture-level synthesis for automatic interconnect pipelining.
DAC 2004: 602-607 |
| 160 | EE | Deming Chen,
Jason Cong,
Fei Li,
Lei He:
Low-power technology mapping for FPGA architectures with dual supply voltages.
FPGA 2004: 109-117 |
| 159 | EE | Jason Cong,
Yiping Fan,
Guoling Han,
Zhiru Zhang:
Application-specific instruction generation for configurable processor architectures.
FPGA 2004: 183-189 |
| 158 | EE | Fei Li,
Yan Lin,
Lei He,
Jason Cong:
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics.
FPGA 2004: 42-50 |
| 157 | EE | Gang Chen,
Jason Cong:
Simultaneous Timing Driven Clustering and Placement for FPGAs.
FPL 2004: 158-167 |
| 156 | EE | Jason Cong,
Jie Wei,
Yan Zhang:
A thermal-driven floorplanning algorithm for 3D ICs.
ICCAD 2004: 306-313 |
| 155 | EE | Chen Li,
Min Xie,
Cheng-Kok Koh,
Jason Cong,
Patrick H. Madden:
Routability-driven placement and white space allocation.
ICCAD 2004: 394-401 |
| 154 | EE | Deming Chen,
Jason Cong:
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs.
ICCAD 2004: 752-759 |
| 153 | EE | Deming Chen,
Jason Cong:
Delay optimal low-power circuit clustering for FPGAs with dual supply voltages.
ISLPED 2004: 70-73 |
| 152 | EE | Jason Cong,
Gabriele Nataneli,
Michail Romesis,
Joseph R. Shinnerl:
An area-optimality study of floorplanning.
ISPD 2004: 78-83 |
| 151 | EE | Jason Cong,
Sung Kyu Lim:
Retiming-based timing analysis with an application to mincut-based global placement.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1684-1692 (2004) |
| 150 | EE | Jason Cong,
Sung Kyu Lim:
Edge separability-based circuit clustering with application to multilevel circuit partitioning.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 346-357 (2004) |
| 149 | EE | Chin-Chih Chang,
Jason Cong,
Michail Romesis,
Min Xie:
Optimality and scalability study of existing placement algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 537-549 (2004) |
| 148 | EE | Jason Cong,
Yiping Fan,
Guoling Han,
Xun Yang,
Zhiru Zhang:
Architecture and synthesis for on-chip multicycle communication.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 550-564 (2004) |
| 2003 |
|---|
| 147 | EE | Jason Cong,
Yiping Fan,
Guoling Han,
Xun Yang,
Zhiru Zhang:
Architecture and synthesis for multi-cycle on-chip communication.
CODES+ISSS 2003: 77-78 |
| 146 | EE | Jason Cong,
Xin Yuan:
Multilevel global placement with retiming.
DAC 2003: 208-213 |
| 145 | EE | Jason Cong,
Ashok Jagannathan,
Glenn Reinman,
Michail Romesis:
Microarchitecture evaluation with physical planning.
DAC 2003: 32-35 |
| 144 | EE | Fei Li,
Deming Chen,
Lei He,
Jason Cong:
Architecture evaluation for power-efficient FPGAs.
FPGA 2003: 175-184 |
| 143 | EE | Tony F. Chan,
Jason Cong,
Tim Kong,
Joseph R. Shinnerl,
Kenton Sze:
An Enhanced Multilevel Algorithm for Circuit Placement.
ICCAD 2003: 299-306 |
| 142 | EE | Jason Cong,
Michail Romesis,
Min Xie:
Optimality and Stability Study of Timing-Driven Placement Algorithms.
ICCAD 2003: 472-479 |
| 141 | EE | Zhiru Zhang,
Yiping Fan,
Miodrag Potkonjak,
Jason Cong:
Gradual Relaxation Techniques with Applications to Behavioral Synthesis.
ICCAD 2003: 529-535 |
| 140 | EE | Jason Cong,
Yiping Fan,
Guoling Han,
Xun Yang,
Zhiru Zhang:
Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication.
ICCAD 2003: 536-543 |
| 139 | EE | Jason Cong,
Tim Kong,
Joseph R. Shinnerl,
Min Xie,
Xin Yuan:
Large-Scale Circuit Placement: Gap and Promise.
ICCAD 2003: 883-890 |
| 138 | EE | Deming Chen,
Jason Cong,
Yiping Fan:
Low-power high-level synthesis for FPGA architectures.
ISLPED 2003: 134-139 |
| 137 | EE | Jason Cong,
Yiping Fan,
Xun Yang,
Zhiru Zhang:
Architecture and synthesis for multi-cycle communication.
ISPD 2003: 190-196 |
| 136 | EE | Jason Cong,
Michail Romesis,
Min Xie:
Optimality, scalability and stability study of partitioning and placement algorithms.
ISPD 2003: 88-94 |
| 135 | EE | Deming Chen,
Jason Cong,
Milos D. Ercegovac,
Zhijun Huang:
Performance-driven mapping for CPLD architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1424-1431 (2003) |
| 134 | EE | Chin-Chih Chang,
Jason Cong,
David Zhigang Pan,
Xin Yuan:
Multilevel global placement with congestion control.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 395-409 (2003) |
| 2002 |
|---|
| 133 | EE | Jason Cong,
Yizhou Lin,
Wangning Long:
SPFD-based global rewiring.
FPGA 2002: 77-84 |
| 132 | EE | Jason Cong,
Min Xie,
Yan Zhang:
An enhanced multilevel routing system.
ICCAD 2002: 51-58 |
| 131 | EE | Jason Cong,
Joey Y. Lin,
Wangning Long:
A new enhanced SPFD rewiring algorithm.
ICCAD 2002: 672-678 |
| 130 | EE | Jason Cong,
Chang Wu:
Global clustering-based performance-driven circuit partitioning.
ISPD 2002: 149-154 |
| 129 | EE | Jason Cong:
Timing closure based on physical hierarchy.
ISPD 2002: 170-174 |
| 128 | EE | Chin-Chih Chang,
Jason Cong,
David Zhigang Pan:
Physical hierarchy generation with routing congestion control.
ISPD 2002: 36-41 |
| 127 | | Jason Cong,
Joey Y. Lin,
Wangning Long:
Enhanced SPFD Rewiring on Improving Rewiring Ability.
IWLS 2002: 91-96 |
| 126 | EE | Jason Cong,
David Zhigang Pan:
Wire width planning for interconnect performance optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(3): 319-329 (2002) |
| 125 | EE | Taku Uchino,
Jason Cong:
An interconnect energy model considering coupling effects.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 763-776 (2002) |
| 2001 |
|---|
| 124 | EE | Jason Cong,
David Zhigang Pan,
Prasanna V. Srinivas:
Improved crosstalk modeling for noise constrained interconnect optimization.
ASP-DAC 2001: 373-378 |
| 123 | EE | Jason Cong,
Michail Romesis:
Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping.
DAC 2001: 389-394 |
| 122 | EE | Taku Uchino,
Jason Cong:
An Interconnect Energy Model Considering Coupling Effects.
DAC 2001: 555-558 |
| 121 | EE | Deming Chen,
Jason Cong,
Milos D. Ercegovac,
Zhijun Huang:
Performance-driven mapping for CPLD architectures.
FPGA 2001: 39-47 |
| 120 | EE | Gang Chen,
Jason Cong:
Simultaneous logic decomposition with technology mapping in FPGA designs.
FPGA 2001: 48-55 |
| 119 | EE | Jason Cong,
Jie Fang,
Yan Zhang VI:
Multilevel Approach to Full-Chip Gridless Routing.
ICCAD 2001: 396-403 |
| 118 | EE | Jason Cong,
Tianming Kong,
Z. D. Pan:
Buffer block planning for interconnect planning and prediction.
IEEE Trans. VLSI Syst. 9(6): 929-937 (2001) |
| 117 | EE | Jason Cong,
Cheng-Kok Koh,
Patrick H. Madden:
Interconnect layout optimization under higher order RLC model forMCM designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(12): 1455-1463 (2001) |
| 116 | EE | Chin-Chih Chang,
Jason Cong:
Pseudopin assignment with crosstalk noise control.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 598-611 (2001) |
| 115 | EE | Jason Cong,
Jie Fang,
Kei-Yong Khoo:
DUNE-a multilayer gridless routing system.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 633-647 (2001) |
| 114 | EE | Jason Cong,
David Zhigang Pan:
Interconnect performance estimation models for design planning.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 739-752 (2001) |
| 113 | EE | Jason Cong,
Yean-Yow Hwang:
Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1077-1090 (2001) |
| 112 | EE | Jason Cong,
Lei He,
Cheng-Kok Koh,
David Zhigang Pan:
Interconnect sizing and spacing with consideration of couplingcapacitance.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1164-1169 (2001) |
| 2000 |
|---|
| 111 | EE | Jason Cong,
Songjie Xu:
Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs.
ASP-DAC 2000: 157-162 |
| 110 | EE | Jason Cong,
Tianming Kong,
Faming Liang,
Jun S. Liu,
Wing Hung Wong,
Dongmin Xu:
Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application.
ASP-DAC 2000: 277-282 |
| 109 | EE | Jason Cong,
Sung Kyu Lim:
Edge separability based circuit clustering with application to circuit partitioning.
ASP-DAC 2000: 429-434 |
| 108 | EE | Jason Cong,
Sung Kyu Lim:
Performance driven multiway partitioning.
ASP-DAC 2000: 441-446 |
| 107 | EE | Maogang Wang,
Sung Lim,
Jason Cong,
Majid Sarrafzadeh:
Multi-way partitioning using bi-partition heuristics.
ASP-DAC 2000: 667 |
| 106 | EE | Jason Cong,
Sung Kyu Lim,
Chang Wu:
Performance driven multi-level and multiway partitioning with retiming.
DAC 2000: 274-279 |
| 105 | EE | Jason Cong,
Hui Huang:
Depth optimal incremental mapping for field programmable gate arrays.
DAC 2000: 290-293 |
| 104 | EE | Jason Cong,
Xin Yuan:
Routing tree construction under fixed buffer locations.
DAC 2000: 379-384 |
| 103 | EE | Jason Cong,
Hui Huang,
Xin Yuan:
Technology mapping for k/m-macrocell based FPGAs.
FPGA 2000: 51-59 |
| 102 | EE | Jason Cong,
Kenneth Yan:
Synthesis for FPGAs with embedded memory blocks.
FPGA 2000: 75-82 |
| 101 | | Tony F. Chan,
Jason Cong,
Tianming Kong,
Joseph R. Shinnerl:
Multilevel Optimization for Large-Scale Circuit Placement.
ICCAD 2000: 171-176 |
| 100 | | Jason Cong,
Sung Kyu Lim:
Physical Planning with Retiming.
ICCAD 2000: 2-7 |
| 99 | | Olivier Coudert,
Jason Cong,
Sharad Malik,
Majid Sarrafzadeh:
Incremental CAD.
ICCAD 2000: 236-243 |
| 98 | EE | Jason Cong,
Jie Fang,
Kei-Yong Khoo:
DUNE: a multi-layer gridless routing system with wire planning.
ISPD 2000: 12-18 |
| 97 | EE | Chin-Chih Chang,
Jason Cong:
Pseudo pin assignment with crosstalk noise control.
ISPD 2000: 41-47 |
| 96 | EE | Jason Cong,
Majid Sarrafzadeh:
Incremental physical design.
ISPD 2000: 84-92 |
| 95 | EE | Jason Cong,
Yean-Yow Hwang:
Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs.
ACM Trans. Design Autom. Electr. Syst. 5(2): 193-225 (2000) |
| 94 | EE | Jason Cong,
Songjie Xu:
Performance-driven technology mapping for heterogeneous FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1268-1281 (2000) |
| 93 | EE | Jason Cong,
Jie Fang,
Kei-Yong Khoo:
Via design rule consideration in multilayer maze routing algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 215-223 (2000) |
| 1999 |
|---|
| 92 | | Farid N. Najm,
Jason Cong,
David Blaauw:
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, San Diego, California, USA, August 16-17, 1999
ACM 1999 |
| 91 | EE | Jason Cong,
Tianming Kong,
Dongmin Xu,
Faming Liang,
Jun S. Liu,
Wing Hung Wong:
Relaxed Simulated Tempering for VLSI Floorplan Designs.
ASP-DAC 1999: 13-16 |
| 90 | EE | Jason Cong,
David Zhigang Pan:
Interconnect Delay Estimation Models for Synthesis and Design Planning.
ASP-DAC 1999: 97-100 |
| 89 | EE | Jason Cong,
Yean-Yow Hwang,
Songjie Xu:
Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections.
DAC 1999: 373-378 |
| 88 | EE | Jason Cong,
Honching Li,
Chang Wu:
Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization.
DAC 1999: 460-465 |
| 87 | EE | Jason Cong,
David Zhigang Pan:
Interconnect Estimation and Dlanning for Deep Submicron Designs.
DAC 1999: 507-510 |
| 86 | EE | Jason Cong,
Chang Wu,
Yuzheng Ding:
Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution.
FPGA 1999: 29-35 |
| 85 | EE | Jason Cong,
Jie Fang,
Kei-Yong Khoo:
An implicit connection graph maze routing algorithm for ECO routing.
ICCAD 1999: 163-167 |
| 84 | EE | Jason Cong,
Tianming Kong,
David Zhigang Pan:
Buffer block planning for interconnect-driven floorplanning.
ICCAD 1999: 358-363 |
| 83 | EE | Jason Cong,
Jie Fang,
Kei-Yong Khoo:
VIA design rule consideration in multi-layer maze routing algorithms.
ISPD 1999: 214-220 |
| 82 | EE | Jason Cong,
Chang Wu:
Optimal FPGA mapping and retiming with efficient initial state computation.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1595-1607 (1999) |
| 81 | EE | Jason Cong,
Lei He:
Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 406-420 (1999) |
| 80 | EE | Chin-Chih Chang,
Jason Cong:
An efficient approach to multilayer layer assignment with anapplication to via minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(5): 608-620 (1999) |
| 1998 |
|---|
| 79 | EE | Jason Cong,
Chang Wu:
Optimal FPGA Mapping and Retiming with Efficient Initial State Computation.
DAC 1998: 330-335 |
| 78 | EE | Jason Cong,
Patrick H. Madden:
Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs.
DAC 1998: 356-361 |
| 77 | EE | Jason Cong,
Songjie Xu:
Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs.
DAC 1998: 704-707 |
| 76 | EE | Jason Cong,
Songjie Xu:
Technology Mapping for FPGAs with Embedded Memory Blocks.
FPGA 1998: 179-188 |
| 75 | EE | Jason Cong,
Yean-Yow Hwang:
Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation.
FPGA 1998: 27-34 |
| 74 | EE | Darko Kirovski,
Yean-Yow Hwang,
Miodrag Potkonjak,
Jason Cong:
Intellectual property protection by watermarking combinational logic synthesis solutions.
ICCAD 1998: 194-198 |
| 73 | EE | Jason Cong,
Songjie Xu:
Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources.
ICCAD 1998: 40-44 |
| 72 | EE | Robert C. Aitken,
Jason Cong,
Randy Harr,
Kenneth L. Shepard,
Wayne Wolf:
How will CAD handle billion-transistor systems? (panel).
ICCAD 1998: 5 |
| 71 | EE | Jason Cong,
Sung Kyu Lim:
Multiway partitioning with pairwise movement.
ICCAD 1998: 512-516 |
| 70 | EE | Jason Cong,
Lei He:
An efficient technique for device and interconnect optimization in deep submicron designs.
ISPD 1998: 45-51 |
| 69 | EE | Jason Cong,
Andrew B. Kahng,
Cheng-Kok Koh,
Chung-Wen Albert Tsao:
Bounded-skew clock and Steiner routing.
ACM Trans. Design Autom. Electr. Syst. 3(3): 341-388 (1998) |
| 68 | EE | Jason Cong,
Andrew B. Kahng,
Kwok-Shing Leung:
Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(1): 24-39 (1998) |
| 67 | EE | Jason Cong,
Chang Wu:
An efficient algorithm for performance-optimal FPGA technology mapping with retiming.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 738-748 (1998) |
| 1997 |
|---|
| 66 | EE | Chin-Chih Chang,
Jason Cong:
An Efficient Approach to Multi-Layer Layer Assignment with Application to Via Minimization.
DAC 1997: 600-603 |
| 65 | EE | Jason Cong,
Lei He,
Andrew B. Kahng,
David Noice,
Nagesh Shirali,
Steve H.-C. Yen:
Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology.
DAC 1997: 627-632 |
| 64 | EE | Jason Cong,
Chang Wu:
FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits.
DAC 1997: 644-649 |
| 63 | EE | Jason Cong,
John Peck:
On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor.
FCCM 1997: 246-248 |
| 62 | EE | Jason Cong,
Yean-Yow Hwang:
Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping.
FPGA 1997: 35-42 |
| 61 | EE | Jason Cong,
Honching Peter Li,
Sung Kyu Lim,
Toshiyuki Shibuya,
Dongmin Xu:
Large scale circuit partitioning with loose/stable net removal and signal flow based clustering.
ICCAD 1997: 441-446 |
| 60 | EE | Jason Cong,
David Zhigang Pan,
Lei He,
Cheng-Kok Koh,
Kei-Yong Khoo:
Interconnect design for deep submicron ICs.
ICCAD 1997: 478-485 |
| 59 | EE | Jason Cong,
Lei He,
Cheng-Kok Koh,
David Zhigang Pan:
Global interconnect sizing and spacing with consideration of coupling capacitance.
ICCAD 1997: 628-633 |
| 58 | EE | Jason Cong,
Cheng-Kok Koh:
Interconnect layout optimization under higher-order RLC model.
ICCAD 1997: 713-720 |
| 57 | EE | Jason Cong,
Patrick H. Madden:
Performance driven global routing for standard cell design.
ISPD 1997: 73-80 |
| 56 | EE | Jason Cong,
Andrew B. Kahng,
Kwok-Shing Leung:
Efficient heuristics for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design.
ISPD 1997: 88-95 |
| 55 | EE | Jason Cong,
Patrick H. Madden:
Performance-driven routing with multiple sources.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(4): 410-419 (1997) |
| 1996 |
|---|
| 54 | EE | Jason Cong,
Yean-Yow Hwang:
Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design.
DAC 1996: 726-729 |
| 53 | EE | Jason Cong,
John Peck,
Yuzheng Ding:
RASP: A General Logic Synthesis System for SRAM-Based FPGAs.
FPGA 1996: 137-143 |
| 52 | EE | Jason Cong,
Lei He:
An efficient approach to simultaneous transistor and interconnect sizing.
ICCAD 1996: 181-186 |
| 51 | EE | Takumi Okamoto,
Jason Cong:
Buffered Steiner tree construction with wire sizing for interconnect layout optimization.
ICCAD 1996: 44-49 |
| 50 | EE | Jason Cong,
Chang Wu:
An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA Desig.
ICCD 1996: 572-578 |
| 49 | EE | Jason Cong,
Cheng-Kok Koh,
Kwok-Shing Leung:
Simultaneous buffer and wire sizing for performance and power optimization.
ISLPED 1996: 271-276 |
| 48 | EE | Jason Cong,
Yuzheng Ding:
Combinational logic synthesis for LUT based field programmable gate arrays.
ACM Trans. Design Autom. Electr. Syst. 1(2): 145-204 (1996) |
| 47 | EE | Jason Cong,
Lei He:
Optimal wiresizing for interconnects with multiple sources.
ACM Trans. Design Autom. Electr. Syst. 1(4): 478-511 (1996) |
| 46 | EE | Jason Cong,
Wilburt Labio,
Narayanan Shivakumar:
Multiway VLSI circuit partitioning based on dual net representation.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(4): 396-409 (1996) |
| 45 | EE | Jason Cong,
Lei He,
Cheng-Kok Koh,
Patrick H. Madden:
Performance optimization of VLSI interconnect layout.
Integration 21(1-2): 1-94 (1996) |
| 1995 |
|---|
| 44 | EE | Jason Cong,
Dongmin Xu:
Exploitation signal flow and logic dependency in standard cell placement.
ASP-DAC 1995 |
| 43 | EE | Jason Cong,
Yean-Yow Hwang:
Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping.
FPGA 1995: 68-74 |
| 42 | EE | Jason Cong,
Yuzheng Ding:
On Nominal Delay Minimization in LUT-based FPGA Technology Mapping.
FPGA 1995: 82-88 |
| 41 | EE | Jason Cong,
Lei He:
Optimal wiresizing for interconnects with multiple sources.
ICCAD 1995: 568-574 |
| 40 | EE | Jason Cong,
Andrew B. Kahng,
Cheng-Kok Koh,
Chung-Wen Albert Tsao:
Bounded-skew clock and Steiner routing under Elmore delay.
ICCAD 1995: 66-71 |
| 39 | | Jason Cong,
Patrick H. Madden:
Performance Driven Routing with Mulitiple Sources.
ISCAS 1995: 203-206 |
| 38 | | Jason Cong,
Cheng-Kok Koh:
Minimum-Cost Bounded-Skew Clock Routing.
ISCAS 1995: 215-218 |
| 37 | EE | Kei-Yong Khoo,
Jason Cong:
An efficient multilayer MCM router based on four-via routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(10): 1277-1290 (1995) |
| 36 | EE | Jason Cong,
Kwok-Shing Leung:
Optimal wiresizing under Elmore delay model.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 321-336 (1995) |
| 1994 |
|---|
| 35 | EE | Jason Cong,
Zheng Li,
Rajive Bagrodia:
Acyclic Multi-Way Partitioning of Boolean Networks.
DAC 1994: 670-675 |
| 34 | EE | Jason Cong,
Cheng-Kok Koh:
Simultaneous driver and wire sizing for performance and power optimization.
ICCAD 1994: 206-212 |
| 33 | EE | Jason Cong,
Wilburt Labio,
Narayanan Shivakumar:
Multi-way VLSI circuit partitioning based on dual net representation.
ICCAD 1994: 56-62 |
| 32 | EE | Rajive Bagrodia,
Zheng Li,
Vikas Jha,
Yuan Chen,
Jason Cong:
Parallel logic level simulation of VLSI circuits.
Winter Simulation Conference 1994: 1354-1361 |
| 31 | EE | Jason Cong,
Yuzheng Ding,
Tong Gao,
Kuang-Chien Chen:
LUT-based FPGA technology mapping under arbitrary net-delay models.
Computers & Graphics 18(4): 507-516 (1994) |
| 30 | EE | Jason Cong,
Yuzheng Ding:
On area/depth trade-off in LUT-based FPGA technology mapping.
IEEE Trans. VLSI Syst. 2(2): 137-148 (1994) |
| 29 | EE | Jason Cong,
Cheng-Kok Koh:
Simultaneous driver and wire sizing for performance and power optimization.
IEEE Trans. VLSI Syst. 2(4): 408-425 (1994) |
| 28 | EE | Jason Cong,
Yuzheng Ding:
FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(1): 1-12 (1994) |
| 1993 |
|---|
| 27 | EE | Jason Cong,
Yuzheng Ding:
On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping.
DAC 1993: 213-218 |
| 26 | EE | Kei-Yong Khoo,
Jason Cong:
An Efficient Multilayer MCM Router Based on Four-Via Routing.
DAC 1993: 590-595 |
| 25 | EE | Jason Cong,
Kwok-Shing Leung,
Dian Zhou:
Performance-Driven Interconnect Design Based on Distributed RC Delay Model.
DAC 1993: 606-611 |
| 24 | EE | Jason Cong,
M'Lissa Smith:
A Parallel Bottom-Up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design.
DAC 1993: 755-760 |
| 23 | EE | Jason Cong,
Yuzheng Ding:
Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs.
ICCAD 1993: 110-114 |
| 22 | EE | Jason Cong,
Kwok-Shing Leung:
Optimal wiresizing under the distributed Elmore delay model.
ICCAD 1993: 634-639 |
| 21 | | Charles J. Alpert,
Jason Cong,
Andrew B. Kahng,
Gabriel Robins,
Majid Sarrafzadeh:
Minimum Density Interconneciton Trees.
ISCAS 1993: 1865-1868 |
| 20 | | Dian Zhou,
S. Su,
F. Tsui,
D. S. Gao,
Jason Cong:
A Two-pole Circuit Model for VLSI High-speed Interconnection.
ISCAS 1993: 2129-2132 |
| 19 | | Jason Cong,
Moazzem Hossain,
Naveed A. Sherwani:
A Provably Good Algorithm for k-Layer Topological Planar Routing Problems.
VLSI Design 1993: 113 |
| 18 | EE | Jason Cong,
Moazzem Hossain,
Naveed A. Sherwani:
A provably good multilayer topological planar routing algorithm in IC layout designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 70-78 (1993) |
| 17 | EE | Jason Cong,
Bryan Preas,
C. L. Liu:
Physical models and efficient algorithms for over-the-cell routing in standard cell design.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 723-734 (1993) |
| 16 | EE | Jason Cong,
Andrew B. Kahng,
Gabriel Robins:
Matching-based methods for high-performance clock routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1157-1169 (1993) |
| 1992 |
|---|
| 15 | EE | Jason Cong,
Lars W. Hagen,
Andrew B. Kahng:
Net Partitions Yield Better Module Partitions.
DAC 1992: 47-52 |
| 14 | EE | Jason Cong,
Yuzheng Ding:
An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs.
ICCAD 1992: 48-53 |
| 13 | | Jason Cong,
Yuzheng Ding,
Andrew B. Kahng,
Peter Trajmar,
Kuang-Chien Chen:
An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization.
ICCD 1992: 154-158 |
| 12 | EE | Kuang-Chien Chen,
Jason Cong,
Yuzheng Ding,
Andrew B. Kahng,
Peter Trajmar:
DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization.
IEEE Design & Test of Computers 9(3): 7-20 (1992) |
| 11 | EE | Jason Cong,
Andrew B. Kahng,
Gabriel Robins,
Majid Sarrafzadeh,
Chak-Kuen Wong:
Provably good performance-driven global routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(6): 739-752 (1992) |
| 1991 |
|---|
| 10 | EE | Andrew B. Kahng,
Jason Cong,
Gabriel Robins:
High-Performance Clock Routing Based on Recursive Geometric Aatching.
DAC 1991: 322-327 |
| 9 | | Jason Cong,
Andrew B. Kahng,
Gabriel Robins,
Majid Sarrafzadeh,
C. K. Wong:
Performance-Driven Global Routing for Cell Based ICs.
ICCD 1991: 170-173 |
| 8 | | Jason Cong,
Kei-Yong Khoo:
A Provable Near-Optimal Algorithm for the Channel Pin Assignment Problem.
ICCD 1991: 319-322 |
| 7 | EE | Jason Cong:
Pin assignment with global routing for general cell designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(11): 1401-1412 (1991) |
| 6 | EE | Khe-Sing The,
Martin D. F. Wong,
Jason Cong:
A layout modification approach to via minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(4): 536-541 (1991) |
| 5 | EE | Jason Cong,
C. L. Liu:
On the k-layer planar subset and topological via minimization problems.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 972-981 (1991) |
| 1990 |
|---|
| 4 | EE | Jason Cong,
Bryan Preas,
C. L. Liu:
General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design.
DAC 1990: 709-715 |
| 3 | EE | Jason Cong,
C. L. Liu:
Over-the-cell channel routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(4): 408-418 (1990) |
| 1989 |
|---|
| 2 | EE | Khe-Sing The,
D. F. Wong,
Jason Cong:
VIA Minimization by Layout Modification.
DAC 1989: 799-802 |
| 1988 |
|---|
| 1 | EE | Jason Cong,
Martin D. F. Wong,
C. L. Liu:
A new approach to three- or four-layer channel routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(10): 1094-1104 (1988) |
