Valentina Ciriani

2008
18	EE	Anna Bernasconi, Valentina Ciriani, Roberto Cordone: The optimization of kEP-SOPs: Computational complexity, approximability and experiments. ACM Trans. Design Autom. Electr. Syst. 13(2): (2008)
2007
17	EE	Anna Bernasconi, Valentina Ciriani, Roberto Cordone: An approximation algorithm for fully testable kEP-SOP networks. ACM Great Lakes Symposium on VLSI 2007: 417-422
16	EE	Valentina Ciriani, Sabrina De Capitani di Vimercati, Sara Foresti, Sushil Jajodia, Stefano Paraboschi, Pierangela Samarati: Fragmentation and Encryption to Enforce Privacy in Data Storage. ESORICS 2007: 171-186
15	EE	Valentina Ciriani, Paolo Ferragina, Fabrizio Luccio, S. Muthukrishnan: A data structure for a sequence of string accesses in external memory. ACM Transactions on Algorithms 3(1): (2007)
2006
14	EE	Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa: Efficient minimization of fully testable 2-SPP networks. DATE 2006: 1300-1305
13	EE	Anna Bernasconi, Valentina Ciriani: DRedSOP: Synthesis of a New Class of Regular Functions. DSD 2006: 377-384
12	EE	Anna Bernasconi, Valentina Ciriani, Roberto Cordone: EXOR Projected Sum of Products. VLSI-SoC 2006: 284-289
11	EE	Valentina Ciriani, Anna Bernasconi, Rolf Drechsler: Testability of SPP Three-Level Logic Networks in Static Fault Models. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2241-2248 (2006)
10	EE	Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli: Exploiting Regularities for Boolean Function Synthesis. Theory Comput. Syst. 39(4): 485-501 (2006)
2004
9	EE	Valentina Ciriani, Nadia Pisanti, Anna Bernasconi: Room allocation: a polynomial subcase of the quadratic assignment problem. Discrete Applied Mathematics 144(3): 263-269 (2004)
2003
8		Valentina Ciriani, Anna Bernasconi, Rolf Drechsler: Testability of SPP Three-Level Logic Networks. VLSI-SOC 2003: 331-336
7	EE	Valentina Ciriani: Synthesis of SPP three-level logic networks using affine spaces. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1310-1323 (2003)
6	EE	Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli: Three-level logic minimization based on function regularities. IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 1005-1016 (2003)
5	EE	Valentina Ciriani, Fabrizio Luccio, Linda Pagli: Synthesis of integer multipliers in sum of pseudoproducts form. Integration 36(3): 103-119 (2003)
2002
4	EE	Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli: Fast three-level logic minimization based on autosymmetry. DAC 2002: 425-430
3	EE	Valentina Ciriani, Paolo Ferragina, Fabrizio Luccio, S. Muthukrishnan: Static Optimality Theorem for External Memory String Access. FOCS 2002: 219-227
2		Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli: Implicit Test of Regularity for Not Completely Specified Boolean Functions. IWLS 2002: 345-350
2001
1	EE	Valentina Ciriani: Logic Minimization using Exclusive OR Gates. DAC 2001: 115-120

Coauthor Index

1	Anna Bernasconi	[2] [4] [6] [8] [9] [10] [11] [12] [13] [14] [17] [18]
2	Roberto Cordone	[12] [17] [18]
3	Rolf Drechsler	[8] [11] [14]
4	Paolo Ferragina	[3] [15]
5	Sara Foresti	[16]
6	Sushil Jajodia	[16]
7	Fabrizio Luccio	[2] [3] [4] [5] [6] [10] [15]
8	S. Muthukrishnan (S. Muthu Muthukrishnan)	[3] [15]
9	Linda Pagli	[2] [4] [5] [6] [10]
10	Stefano Paraboschi	[16]
11	Nadia Pisanti	[9]
12	Pierangela Samarati	[16]
13	Tiziano Villa	[14]
14	Sabrina De Capitani di Vimercati	[16]

Colors in the list of coauthors