| |
| * | 1998 | |
|---|---|---|
| 1 | EE | Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen, Hsien-Ho Chuang: On circuit clustering for area/delay tradeoff under capacity and pin constraints. IEEE Trans. VLSI Syst. 6(4): 634-642 (1998) |
| 1 | Juinn-Dar Huang | [1] |
| 2 | Jing-Yang Jou | [1] |
| 3 | Wen-Zen Shen | [1] |