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Chris C. N. Chu Vis

Chris Chu, Chris Chong-Nuen Chu

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*2009
64EEYue Xu, Yanheng Zhang, Chris Chu: FastRoute 4.0: global router with efficient via minimization. ASP-DAC 2009: 576-581
63EEJackey Z. Yan, Natarajan Viswanathan, Chris Chu: Handling complexities in modern large-scale mixed-size placement. DAC 2009: 436-441
62EESteve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu: Handling routability in floorplan design with twin binary trees. Integration 42(4): 449-456 (2009)
2008
61EEJackey Z. Yan, Chris Chu: DeFer: deferred decision making enabled fixed-outline floorplanner. DAC 2008: 161-166
60EEYanheng Zhang, Yue Xu, Chris Chu: FastRoute3.0: a fast and high quality global router based on virtual capacity. ICCAD 2008: 344-349
59EEChris Chu: Wire Sizing. Encyclopedia of Algorithms 2008
58EEChris C. N. Chu, Yiu-Chung Wong: FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 70-83 (2008)
2007
57EENatarajan Viswanathan, Min Pan, Chris C. N. Chu: FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control. ASP-DAC 2007: 135-140
56EEMin Pan, Chris C. N. Chu, Priyadarshan Patra: A Novel Performance-Driven Topology Design Algorithm. ASP-DAC 2007: 244-249
55EEMin Pan, Chris C. N. Chu: FastRoute 2.0: A High-quality and Efficient Global Router. ASP-DAC 2007: 250-255
54EENatarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris C. N. Chu: RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. DAC 2007: 453-458
53EEMin Pan, Chris C. N. Chu: IPR: An Integrated Placement and Routing Algorithm. DAC 2007: 59-62
52EECharles J. Alpert, Chris C. N. Chu, Paul G. Villarrubia: The coming of age of physical synthesis. ICCAD 2007: 246-249
51EEDennis K. Y. Tong, Evangeline F. Y. Young, Chris C. N. Chu, Sampath Dechu: Wire Retiming Problem With Net Topology Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1648-1660 (2007)
2006
50EENatarajan Viswanathan, Min Pan, Chris C. N. Chu: FastPlace 2.0: an efficient analytical placer for mixed-mode designs. ASP-DAC 2006: 195-200
49EEChiu-Wing Sham, Evangeline F. Y. Young, Chris C. N. Chu: Optimal cell flipping in placement and floorplanning. DAC 2006: 1109-1114
48EEChuan Lin, Hai Zhou, Chris C. N. Chu: A revisit to floorplan optimization by Lagrangian relaxation. ICCAD 2006: 164-171
47EEYiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N. Chu: Analog placement with symmetry and other placement constraints. ICCAD 2006: 349-354
46EEMin Pan, Chris C. N. Chu: FastRoute: a step to integrate global routing into placement. ICCAD 2006: 464-471
45EERoyce L. S. Ching, Evangeline F. Y. Young, Kevin C. K. Leung, Chris C. N. Chu: Post-placement voltage island generation. ICCAD 2006: 641-646
2005
44 Min Pan, Natarajan Viswanathan, Chris C. N. Chu: An efficient and effective detailed placement algorithm. ICCAD 2005: 48-55
43EEZion Cien Shen, Chris C. N. Chu, Ying-Meng Li: Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages. ICCD 2005: 38-44
42EEMin Pan, Chris C. N. Chu, J. Morris Chang: Transition time bounded low-power clock tree construction. ISCAS (3) 2005: 2445-2448
41EEMin Pan, Chris C. N. Chu, Hai Zhou: Timing yield estimation using statistical static timing analysis. ISCAS (3) 2005: 2461-2464
40EENatarajan Viswanathan, Min Pan, Chris C. N. Chu: FastPlace: an analytical placer for mixed-mode designs. ISPD 2005: 221-223
39EEChris C. N. Chu, Yiu-Chung Wong: Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design. ISPD 2005: 28-35
38EESampath Dechu, Zion Cien Shen, Chris C. N. Chu: An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 600-608 (2005)
37EENatarajan Viswanathan, Chris C. N. Chu: FastPlace: efficient analytical placement using cell shifting, iterative local refinement, and a hybrid net model. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 722-733 (2005)
2004
36EESampath Dechu, Zion Cien Shen, Chris C. N. Chu: An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations. ASP-DAC 2004: 361-366
35EEZion Cien Shen, Chris C. N. Chu: Accurate and efficient flow based congestion estimation in floorplanning. ASP-DAC 2004: 671-676
34EEDebjit Sinha, Hai Zhou, Chris C. N. Chu: Optimal gate sizing for coupling-noise reduction. ISPD 2004: 176-181
33EENatarajan Viswanathan, Chris C. N. Chu: FastPlace: efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. ISPD 2004: 26-33
32EEArif Ishaq Abou-Seido, Brian Nowak, Chris Chong-Nuen Chu: Fitted Elmore delay: a simple and accurate interconnect delay model. IEEE Trans. VLSI Syst. 12(7): 691-696 (2004)
31EEEvangeline F. Y. Young, Chris C. N. Chu, M. L. Ho: Placement constraints in floorplan design. IEEE Trans. VLSI Syst. 12(7): 735-745 (2004)
30EECharles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay: Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 136-141 (2004)
29EEChris C. N. Chu, Evangeline F. Y. Young: Nonrectangular shaping and sizing of soft modules for floorplan-design improvement. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 71-79 (2004)
2003
28EESteve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu: A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees. DATE 2003: 10856-10861
27EEChris C. N. Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, Sampath Dechu: Retiming with Interconnect and Gate Delay. ICCAD 2003: 221-226
26EEZion Cien Shen, Chris C. N. Chu: Bounds on the number of slicing, mosaic, and general floorplans. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1354-1361 (2003)
25EEEvangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen: Twin binary sequences: a nonredundant representation for general nonslicing floorplan. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 457-469 (2003)
24EEDaniel Berleant, Mei-Peng Cheong, Chris C. N. Chu, Yong Guan, Ahmed Kamal, Gerald Shedblé, Scott Ferson, James F. Peters: Dependable Handling of Uncertainty. Reliable Computing 9(6): 407-418 (2003)
2002
23EEChris C. N. Chu, Evangeline F. Y. Young: Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design. DATE 2002: 1101
22EEArif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Chu: Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model. ICCD 2002: 422-427
21EECharles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay: Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. ISPD 2002: 104-109
20EEEvangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen: Twin binary sequences: a non-redundant representation for general non-slicing floorplan. ISPD 2002: 196-201
19EEEvangeline F. Y. Young, Chris C. N. Chu, M. L. Ho: A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design. VLSI Design 2002: 661-
2001
18EEChris C. N. Chu, D. F. Wong: Closed form solutions to simultaneous buffer insertion/sizing and wire sizing. ACM Trans. Design Autom. Electr. Syst. 6(3): 343-371 (2001)
17EEChris C. N. Chu, D. F. Wong: VLSI Circuit Performance Optimization by Geometric Programming. Annals OR 105(1-4): 37-60 (2001)
16EEYu-Yen Mo, Chris C. N. Chu: Hybrid dynamic/quadratic programming algorithm for interconnecttree optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 680-686 (2001)
15EEEvangeline F. Y. Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong: Handling soft modules in general nonslicing floorplan usingLagrangian relaxation. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 687-692 (2001)
2000
14EEYu-Yen Mo, Chris C. N. Chu: A hybrid dynamic/quadratic programming algorithm for interconnect tree optimization. ISPD 2000: 134-139
13EEFung Yu Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong: Floorplan area minimization using Lagrangian relaxation. ISPD 2000: 174-179
1999
12EEChris C. N. Chu, Martin D. F. Wong: Greedy wire-sizing is linear time. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 398-405 (1999)
11EEChris C. N. Chu, Martin D. F. Wong: A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 787-798 (1999)
10EEChung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong: Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. IEEE Trans. on CAD of Integrated Circuits and Systems 18(7): 1014-1025 (1999)
9EEChris C. N. Chu, Martin D. F. Wong: An efficient and optimal algorithm for simultaneous buffer and wire sizing. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1297-1304 (1999)
8EEFung Yu Young, Chris C. N. Chu, D. F. Wong: Generation of Universal Series-Parallel Boolean Functions. J. ACM 46(3): 416-435 (1999)
1998
7EEChris C. N. Chu, D. F. Wong: A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing. DATE 1998: 479-
6EEChung-Ping Chen, Chris C. N. Chu, D. F. Wong: Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. ICCAD 1998: 617-624
5EEChris C. N. Chu, D. F. Wong: Greedy wire-sizing is linear time. ISPD 1998: 39-44
4EEChris C. N. Chu, Martin D. F. Wong: A matrix synthesis approach to thermal placement. IEEE Trans. on CAD of Integrated Circuits and Systems 17(11): 1166-1174 (1998)
1997
3EEChris C. N. Chu, D. F. Wong: A new approach to simultaneous buffer insertion and wire sizing. ICCAD 1997: 614-621
2EEChris C. N. Chu, D. F. Wong: A matrix synthesis approach to thermal placement. ISPD 1997: 163-168
1EEChris C. N. Chu, D. F. Wong: Closed form solution to simultaneous buffer insertion/sizing and wire sizing. ISPD 1997: 192-197

Coauthor Index

1Arif Ishaq Abou-Seido [22] [32]
2Charles J. Alpert [21] [30] [52] [54]
3Daniel Berleant [24]
4J. Morris Chang [42]
5Charlie Chung-Ping Chen (Chung-Ping Chen) [6] [10]
6Mei-Peng Cheong [24]
7Royce L. S. Ching [45]
8Sampath Dechu [27] [36] [38] [51]
9Scott Ferson [24]
10Gopal Gandham [21] [30]
11Yong Guan [24]
12M. L. Ho [19] [31]
13Milos Hrkic [21] [30]
14Jiang Hu [21] [30]
15Ahmed Kamal [24]
16Chandramouli V. Kashyap [21] [30]
17Steve T. W. Lai [28] [62]
18Kevin C. K. Leung [45]
19Ying-Meng Li [43]
20Chuan Lin [48]
21W. S. Luk [13] [15]
22Yu-Yen Mo [14] [16]
23Gi-Joon Nam [54]
24Brian Nowak [22] [32]
25Min Pan [40] [41] [42] [44] [46] [50] [53] [55] [56] [57]
26Priyadarshan Patra [56]
27James F. Peters [24]
28Stephen T. Quay [21] [30]
29Haoxing Ren [54]
30Chiu-Wing Sham [49]
31Gerald Shedblé [24]
32Zion Cien Shen [20] [25] [26] [35] [36] [38] [43]
33Debjit Sinha [34]
34Yiu-Cheong Tam [47]
35Dennis K. Y. Tong [27] [51]
36Paul G. Villarrubia (Paul Villarrubia) [52] [54]
37Natarajan Viswanathan [33] [37] [40] [44] [50] [54] [57] [63]
38Martin D. F. Wong (D. F. Wong) [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [17] [18]
39Y. C. Wong [13] [15]
40Yiu-Chung Wong [39] [58]
41Yue Xu [60] [64]
42Jackey Z. Yan [61] [63]
43Evangeline F. Y. Young (F. Y. Young, Fung Yu Young) [8] [13] [15] [19] [20] [23] [25] [27] [28] [29] [31] [45] [47] [49] [51] [62]
44Yanheng Zhang [60] [64]
45Hai Zhou [34] [41] [48]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)