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* | 2009 | |
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47 | Paul Chow, Peter Y. K. Cheung: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009 ACM 2009 | |

46 | EE | Daniel L. Ly, Paul Chow: A high-performance FPGA architecture for restricted boltzmann machines. FPGA 2009: 73-82 |

2008 | ||

45 | Mike Hutton, Paul Chow: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008 ACM 2008 | |

44 | EE | Andrew W. H. House, Paul Chow: Investigation of Programming Models for Emerging FPGA-Based High Performance Computing Systems. FCCM 2008: 291-292 |

43 | EE | Alexander Kaganov, Paul Chow, Asif Lakhany: FPGA acceleration of Monte-Carlo based credit derivative pricing. FPL 2008: 329-334 |

42 | EE | Tor M. Aamodt, Paul Chow: Compile-time and instruction-set methods for improving floating- to fixed-point conversion accuracy. ACM Trans. Embedded Comput. Syst. 7(3): (2008) |

2007 | ||

41 | EE | Chichyang Chen, Paul Chow: Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor. ACM Great Lakes Symposium on VLSI 2007: 540-545 |

40 | Sam Lee, Paul Chow: An FPGA Implementation of Reciprocal Sums for SPME. ERSA 2007: 159-165 | |

39 | EE | Paul Chow, Mike Hutton: Integrating FPGAs in high-performance computing: introduction. FPGA 2007: 131 |

38 | EE | Tor M. Aamodt, Paul Chow: Optimization of data prefetch helper threads with path-expression based statistical modeling. ICS 2007: 210-221 |

37 | EE | Lesley Shannon, Paul Chow: SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse. IEEE Trans. VLSI Syst. 15(4): 377-390 (2007) |

36 | EE | Manuel Saldaña, Lesley Shannon, Jia Shuo Yue, Sikang Bian, John Craig, Paul Chow: Routability of Network Topologies in FPGAs. IEEE Trans. VLSI Syst. 15(8): 948-951 (2007) |

2006 | ||

35 | EE | Arun Patel, Christopher A. Madill, Manuel Saldaña, Chris Comis, Regis Pomes, Paul Chow: A Scalable FPGA-based Multiprocessor. FCCM 2006: 111-120 |

34 | EE | Manuel Saldaña, Lesley Shannon, Paul Chow: The routability of multiprocessor network topologies in FPGAs. FPGA 2006: 232 |

33 | EE | Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow: A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification. FPL 2006: 1-6 |

32 | EE | Manuel Saldaña, Paul Chow: TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs. FPL 2006: 1-6 |

31 | EE | Manuel Saldaña, Lesley Shannon, Paul Chow: The routability of multiprocessor network topologies in FPGAs. SLIP 2006: 49-56 |

2005 | ||

30 | EE | Lesley Shannon, Paul Chow: Simplifying the Integration of Processing Elements in Computing Systems Using a Programmable Controller. FCCM 2005: 63-72 |

29 | Lesley Shannon, Paul Chow: Leveraging Reconfigurability in the Design Process. FPL 2005: 731-732 | |

28 | Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow: Designing an FPGA SoC Using a Standardized IP Block Interface. FPT 2005: 341-342 | |

2004 | ||

27 | EE | Navid Azizi, Ian Kuon, Aaron Egier, Ahmad Darabiha, Paul Chow: Reconfigurable Molecular Dynamics Simulator. FCCM 2004: 197-206 |

26 | EE | Lesley Shannon, Paul Chow: Using reconfigurability to achieve real-time profiling for hardware/software codesign. FPGA 2004: 190-199 |

25 | EE | Ian Kuon, Navid Azizi, Ahmad Darabiha, Aaron Egier, Paul Chow: FPGA-based supercomputing: an implementation for molecular dynamics. FPGA 2004: 253 |

24 | EE | Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang, John Paul Shen: Hardware Support for Prescient Instruction Prefetch. HPCA 2004: 84-95 |

2003 | ||

23 | EE | Lesley Shannon, Paul Chow: Standardizing the Performance Assessment of Reconfigurable Processor Architectures. FCCM 2003: 282-283 |

22 | EE | Tor M. Aamodt, Pedro Marcuello, Paul Chow, Antonio González, Per Hammarlund, Hong Wang, John Paul Shen: A framework for modeling and optimization of prescient instruction prefetch. SIGMETRICS 2003: 13-24 |

2001 | ||

21 | EE | Jorge E. Carrillo, Paul Chow: The effect of reconfigurable units in superscalar processors. FPGA 2001: 141-150 |

2000 | ||

20 | EE | Tor M. Aamodt, Paul Chow: Embedded ISA support for enhanced floating-point to fixed-point ANSI-C compilation. CASES 2000: 128-137 |

19 | EE | L. Louis Zhang, Brent Beacham, Massoud R. Hashemi, Paul Chow, Alberto Leon-Garcia: A Scheduler ASIC for a Programmable Packet Switch. IEEE Micro 20(1): 42-48 (2000) |

1999 | ||

18 | EE | Ivan Hamer, Paul Chow: DES Cracking on the Transmogrifier 2a. CHES 1999: 13-24 |

17 | EE | Jeffrey A. Jacob, Paul Chow: Memory Interfacing and Instruction Specification for Reconfigurable Processors. FPGA 1999: 145-154 |

16 | Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic: The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning. International Journal of Parallel Programming 27(5): 327-356 (1999) | |

1998 | ||

15 | EE | David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow: The Transmogrifier-2: a 1 million gate rapid-prototyping system. IEEE Trans. VLSI Syst. 6(2): 188-198 (1998) |

1997 | ||

14 | EE | David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow: The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System. FPGA 1997: 53-61 |

13 | EE | Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic: Memory-System Design Considerations for Dynamically-Scheduled Processors. ISCA 1997: 133-143 |

12 | EE | Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic: The Multicluster Architecture: Reducing Cycle Time Through Partitioning. MICRO 1997: 149-159 |

1996 | ||

11 | Mazen A. R. Saghir, Paul Chow, Corinna G. Lee: Exploiting Dual Data-Memory Banks in Digital Signal Processors. ASPLOS 1996: 234-243 | |

10 | EE | Keith I. Farkas, Norman P. Jouppi, Paul Chow: Register File Design Considerations in Dynamically Scheduled Processors. HPCA 1996: 40-51 |

1995 | ||

9 | EE | Paul Chow, P. Glenn Gulak, Paul Chow: A Field-Programmable Mixed-Analog-Digital Array. FPGA 1995: 104-109 |

8 | EE | Paul Chow, P. Glenn Gulak, Paul Chow: A Field-Programmable Mixed-Analog-Digital Array. FPGA 1995: 104-109 |

7 | Keith I. Farkas, Norman P. Jouppi, Paul Chow: How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors? HPCA 1995: 78-89 | |

1994 | ||

6 | Gennady Feygin, P. Glenn Gulak, Paul Chow: Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression. Data Compression Conference 1994: 254-263 | |

5 | Gennady Feygin, P. Glenn Gulak, Paul Chow: Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding. Inf. Process. Manage. 30(6): 805-816 (1994) | |

1993 | ||

4 | Gennady Feygin, P. Glenn Gulak, Paul Chow: Minimizing Error and VLSI Complexity in the Multiplication-Free Approximation of Arithmetic Coding. Data Compression Conference 1993: 118-127 | |

3 | Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton: A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. ISCAS 1993: 1945-1948 | |

1987 | ||

2 | Paul Chow, Mark Horowitz: Architectural Tradeoffs in the Design of MIPS-X. ISCA 1987: 300-308 | |

1983 | ||

1 | Paul Chow, Zvonko G. Vranesic, Jui Lin Yen: A Pipelined Distributed Arithmetic PFFT Processor. IEEE Trans. Computers 32(12): 1128-1136 (1983) |