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Wu-Tung Cheng Vis

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*2009
46EEXun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy: Improving compressed test pattern generation for multiple scan chain failure diagnosis. DATE 2009: 1000-1005
2008
45EEElif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak: Reducing Scan Shift Power at RTL. VTS 2008: 139-146
44EEStefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng: Automatic Test Pattern Generation for Interconnect Open Defects. VTS 2008: 181-186
43EEYu Huang, Ruifeng Guo, Wu-Tung Cheng, James Chien-Mo Li: Survey of Scan Chain Diagnosis. IEEE Design & Test of Computers 25(3): 240-248 (2008)
42EEJanusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Neelanjan Mukherjee, Mark Kassab: X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 147-159 (2008)
2007
41EEWei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang: Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary. VTS 2007: 225-230
40EEJerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai: X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. IEEE Design & Test of Computers 24(5): 476-485 (2007)
2006
39EEWei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang: On Methods to Improve Location Based Logic Diagnosis. VLSI Design 2006: 181-187
2005
38EEYu Huang, Wu-Tung Cheng, Greg Crowell: Using fault model relaxation to diagnose real scan chain defects. ASP-DAC 2005: 1176-1179
37EEWei Zou, Wu-Tung Cheng, Sudhakar M. Reddy: Bridge Defect Diagnosis with Physical Information. Asian Test Symposium 2005: 248-253
36EEJay Jahangiri, Nilanjan Mukherjee, Wu-Tung Cheng, Subramanian Mahadevan, Ron Press: Achieving High Test Quality with Reduced Pin Count Testing. Asian Test Symposium 2005: 312-317
35EELiyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng: Hardware Ef.cient LBISTWith Complementary Weights. ICCD 2005: 479-484
2004
34EEWu-Tung Cheng, Kun-Han Tsai, Yu Huang, Nagesh Tamarapalli, Janusz Rajski: Compactor Independent Direct Diagnosis. Asian Test Symposium 2004: 204-209
33EEYu Huang, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung: Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis. DATE 2004: 1072-1077
32EELiyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng: Logic BIST with Scan Chain Segmentation. ITC 2004: 57-66
31EEXiaogang Du, Sudhakar M. Reddy, Wu-Tung Cheng, Joseph Rayhawk, Nilanjan Mukherjee: At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories. VLSI Design 2004: 895-900
30EELiyang Lai, Thomas Rinderknecht, Wu-Tung Cheng, Janak H. Patel: Logic BIST Using Constrained Scan Cells. VTS 2004: 199-205
29EEXiaogang Du, Sudhakar M. Reddy, Don E. Ross, Wu-Tung Cheng, Joseph Rayhawk: Memory BIST Using ESP. VTS 2004: 243-248
2003
28EEXiaogang Du, Sudhakar M. Reddy, Joseph Rayhawk, Wu-Tung Cheng: Testing Delay Faults in Embedded CAMs. Asian Test Symposium 2003: 378-383
27EEYu Huang, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung: Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults. Asian Test Symposium 2003: 44-49
26EEYu Huang, Wu-Tung Cheng: Using embedded infrastructure IP for SOC post-silicon verification. DAC 2003: 674-677
25EEYu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Sudhakar M. Reddy: Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets. ISQED 2003: 99-104
24EEWu-Tung Cheng: Silicon Diagnosis. ITC 2003: 1305
23EEYu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Cheng-Ju Hsieh, Yu-Ting Hung: Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault. ITC 2003: 319-328
22EETheo J. Powell, Wu-Tung Cheng, Joseph Rayhawk, Omer Samman, Paul Policke, Sherry Lai: BIST for Deep Submicron ASIC Memories with High Performance Application. ITC 2003: 386-392
2002
21EEYu Huang, Sudhakar M. Reddy, Wu-Tung Cheng: Core - Clustering Based SOC Test Scheduling Optimization. Asian Test Symposium 2002: 405-410
20EEYu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan: Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. ITC 2002: 74-82
19EEYu Huang, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy: Constraint Driven Pin Mapping for Concurrent SOC Testing. VLSI Design 2002: 511-516
18EEYu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy: Synthesis of Scan Chains for Netlist Descriptions at RT-Level. J. Electronic Testing 18(2): 189-201 (2002)
17EEYu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy: On Concurrent Test of Core-Based SOC Design. J. Electronic Testing 18(4-5): 401-414 (2002)
2001
16EEYu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy: Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D. Asian Test Symposium 2001: 265-
15 Yu Huang, Chien-Chung Tsai, Neelanjan Mukherjee, Omer Samman, Dan Devries, Wu-Tung Cheng, Sudhakar M. Reddy: On RTL scan design. ITC 2001: 728-737
2000
14EEWu-Tung Cheng: Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng. Asian Test Symposium 2000: 10-
13EEXijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy: SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. VTS 2000: 205-212
1999
12 Wu-Tung Cheng: High time for high level ATPG. ITC 1999: 1113
1996
11 Bejoy G. Oomman, Wu-Tung Cheng, John A. Waicukauski: A Universal Technique for Accelerating Simulation of Scan Test Patterns. ITC 1996: 135-141
1992
10EEThomas M. Niermann, Wu-Tung Cheng, Janak H. Patel: PROOFS: a fast, memory-efficient sequential circuit fault simulator. IEEE Trans. on CAD of Integrated Circuits and Systems 11(2): 198-207 (1992)
9EEWu-Tung Cheng, James L. Lewandowski, Eleanor Wu: Optimal diagnostic methods for wiring interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 11(9): 1161-1166 (1992)
1990
8EEThomas M. Niermann, Wu-Tung Cheng, Janak H. Patel: Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator. DAC 1990: 535-540
7EEWu-Tung Cheng, Janak H. Patel: PROOFS: a super fast fault simulator for sequential circuits. EURO-DAC 1990: 475-479
6EEWu-Tung Cheng, Meng-Lin Yu: Differential fault simulation for sequential circuits. J. Electronic Testing 1(1): 7-13 (1990)
1989
5EEWu-Tung Cheng, Meng-Lin Yu: Differential Fault Simulation - a Fast Method Using Minimal Memory. DAC 1989: 424-428
4 Wu-Tung Cheng, Tapan J. Chakraborty: Gentest: An Automatic Test-Generation System for Sequential Circuits. IEEE Computer 22(4): 43-49 (1989)
1988
3EEWu-Tung Cheng: Split Circuit Model for Test Generation. DAC 1988: 96-101
1987
2 Wu-Tung Cheng, Janak H. Patel: A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders. IEEE Trans. Computers 36(7): 891-895 (1987)
1985
1 Wu-Tung Cheng, Janak H. Patel: Multiple-Fault Detection in Iterative Logic Arrays. ITC 1985: 493-499

Coauthor Index

1Elif Alpaslan [45]
2Bernd Becker [44]
3Tapan J. Chakraborty [4]
4Greg Crowell [38]
5Dan Devries [15]
6Xiaogang Du [28] [29] [31]
7Jennifer Dworak [45]
8Piet Engelke [44]
9Ruifeng Guo [43] [46]
10Cheng-Ju Hsieh [23] [27] [33]
11Alou Huang [27] [33]
12Yu Huang [15] [16] [17] [18] [19] [20] [21] [23] [25] [26] [27] [33] [34] [38] [43] [45]
13Yu-Ting Hung [23] [27] [33]
14Jay Jahangiri [36]
15Mark Kassab [40] [42]
16Martin Keim [44]
17Liyang Lai [30] [32] [35] [40]
18Sherry Lai [22]
19James L. Lewandowski [9]
20Chien-Mo James Li (James Chien-Mo Li) [43]
21Xijiang Lin [13] [45]
22Subramanian Mahadevan [36]
23Grzegorz Mrugalski [40] [42]
24Neelanjan Mukherjee [15] [42]
25Nilanjan Mukherjee [16] [17] [18] [19] [20] [25] [31] [36] [40]
26Thomas M. Niermann [8] [10]
27Bejoy G. Oomman [11]
28Janak H. Patel [1] [2] [7] [8] [10] [30] [32] [35]
29Ilia Polian [44]
30Paul Policke [22]
31Irith Pomeranz [13]
32Theo J. Powell [22]
33Ron Press [36]
34Janusz Rajski [34] [40] [42]
35Joseph Rayhawk [22] [28] [29] [31]
36Sudhakar M. Reddy [13] [15] [16] [17] [18] [19] [20] [21] [23] [25] [28] [29] [31] [37] [39] [41] [46]
37Paul Reuter [20]
38Thomas Rinderknecht [30] [32] [35]
39Don E. Ross [29]
40Omer Samman [15] [16] [17] [18] [19] [20] [22]
41Manish Sharma [40]
42Stefan Spinner [44]
43Nagesh Tamarapalli [34]
44Huaxing Tang [39] [41]
45Xun Tang [46]
46Chien-Chung Tsai [15] [16] [17] [18] [19] [20] [25]
47Kun-Han Tsai [34]
48Huan-Yung Tseng [27] [33]
49Jerzy Tyszer [40] [42]
50John A. Waicukauski [11]
51Eleanor Wu [9]
52Meng-Lin Yu [5] [6]
53Yahya Zaidan [16] [17] [19] [20]
54Yanping Zhang [19]
55Wei Zou [37] [39] [41]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)