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Lerong Cheng Vis

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*2009
18EELerong Cheng, Puneet Gupta, Lei He: Accounting for non-linear dependence using function driven component analysis. ASP-DAC 2009: 474-479
17EELerong Cheng, Puneet Gupta, Costas J. Spanos, Kun Qian, Lei He: Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability. DAC 2009: 104-109
16EELerong Cheng, Jinjun Xiong, Lei He: Non-Gaussian Statistical Timing Analysis Using Second-Order Polynomial Fitting. IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 130-140 (2009)
2008
15EELerong Cheng, Jinjun Xiong, Lei He: Non-Gaussian statistical timing analysis using second-order polynomial fitting. ASP-DAC 2008: 298-303
14EELerong Cheng, Yan Lin, Lei He: Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. FPGA 2008: 159-168
13EELerong Cheng, Xiaoyu Song, Guowu Yang, William N. N. Hung, Zhiwei Tang, Shaodi Gao: A fast congestion estimator for routing with bounded detours. Integration 41(3): 360-370 (2008)
2007
12EELerong Cheng, Jinjun Xiong, Lei He: Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources. DAC 2007: 250-255
11EELerong Cheng, Fei Li, Yan Lin, Phoebe Wong, Lei He: Device and Architecture Cooptimization for FPGA Power Reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1211-1221 (2007)
2006
10EELerong Cheng, Jinjun Xiong, Lei He, Mike Hutton: FPGA Performance Optimization Via Chipwise Placement Considering Process Variations. FPL 2006: 1-6
9EEMing Gu, Fei He, Lerong Cheng, Xiaoyu Song, Guowu Yang: Congestion estimation for hexagonal routing. Int. J. Comput. Math. 83(3): 263-272 (2006)
2005
8EELerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He: Device and architecture co-optimization for FPGA power reduction. DAC 2005: 915-920
7 Ho-Yan Wong, Lerong Cheng, Yan Lin, Lei He: FPGA device and architecture evaluation considering process variations. ICCAD 2005: 19-24
6EEFei He, Xiaoyu Song, Lerong Cheng, Guowu Yang, Zhiwei Tang, Ming Gu, Jia-Guang Sun: A Hierachical Method for Wiring and Congestion Prediction. ISVLSI 2005: 307-308
5EEFei He, Ming Gu, Xiaoyu Song, Zhiwei Tang, Guowu Yang, Lerong Cheng: Probabilistic Estimation for Routing Space. Comput. J. 48(6): 667-676 (2005)
4EEFei He, Lerong Cheng, Guowu Yang, Xiaoyu Song, Ming Gu, Jia-Guang Sun: On Theoretical Upper Bounds for Routing Estimation. J. UCS 11(6): 916-925 (2005)
2004
3EELerong Cheng, Xiaoyu Song, Guowu Yang, Zhiwei Tang: A fast congestion estimator for routing with bounded detours. ASP-DAC 2004: 666-670
2EELerong Cheng, William N. N. Hung, Guowu Yang, Xiaoyu Song: Congestion Estimation for 3D Routing. ISVLSI 2004: 239-240
1EEWilliam N. N. Hung, Xiaoyu Song, T. Kam, Lerong Cheng, Guowu Yang: Routability checking for three-dimensional architectures. IEEE Trans. VLSI Syst. 12(12): 1371-1374 (2004)

Coauthor Index

1Shaodi Gao [13]
2Ming Gu [4] [5] [6] [9]
3Puneet Gupta [17] [18]
4Fei He [4] [5] [6] [9]
5Lei He [7] [8] [10] [11] [12] [14] [15] [16] [17] [18]
6William N. N. Hung [1] [2] [13]
7Michael Hutton (Michael D. Hutton, Mike Hutton) [10]
8T. Kam [1]
9Fei Li [8] [11]
10Yan Lin [7] [8] [11] [14]
11Kun Qian [17]
12Xiaoyu Song [1] [2] [3] [4] [5] [6] [9] [13]
13Costas J. Spanos [17]
14Jia-Guang Sun (Jiaguang Sun) [4] [6]
15Zhiwei Tang [3] [5] [6] [13]
16Ho-Yan Wong [7]
17Phoebe Wong [8] [11]
18Jinjun Xiong [10] [12] [15] [16]
19Guowu Yang [1] [2] [3] [4] [5] [6] [9] [13]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)