| * | 2009 |
|---|
| 8 | | Yean-Ru Chen,
To-Yu Chen,
Pao-Ann Hsiung,
Sao-Jie Chen,
Yu Hen Hu:
Compositional Automata Reduction with Non-critical Path Slicing.
FCS 2009: 133-138 |
| 7 | EE | Pao-Ann Hsiung,
Chao-Sheng Lin,
Shang-Wei Lin,
Yean-Ru Chen,
Chun-Hsien Lu,
Sheng-Ya Tong,
Wan-Ting Su,
Chihhsiong Shih,
Chorng-Shiuh Koong,
Nien-Lin Hsueh,
Chih-Hung Chang,
William C. Chu:
VERTAF/Multi-Core: A SysML-Based Application Framework for Multi-Core Embedded Software Development.
ICA3PP 2009: 303-314 |
| 6 | EE | Pao-Ann Hsiung,
Shang-Wei Lin,
Yean-Ru Chen,
Chun-Hsian Huang,
Chihhsiong Shih,
William C. Chu:
Modeling and verification of real-time embedded systems with urgency.
Journal of Systems and Software 82(10): 1627-1641 (2009) |
| 2007 |
|---|
| 5 | EE | Yean-Ru Chen,
Pao-Ann Hsiung,
Sao-Jie Chen:
Modeling and Automatic Failure Analysis of Safety-Critical Systems Using Extended Safecharts.
SAFECOMP 2007: 451-464 |
| 4 | EE | Pao-Ann Hsiung,
Yean-Ru Chen,
Yen-Hung Lin:
Model Checking Safety-Critical Systems Using Safecharts.
IEEE Trans. Computers 56(5): 692-705 (2007) |
| 3 | EE | Yean-Ru Chen,
Pao-Ann Hsiung:
Automatic Failure Analysis Using Safecharts.
International Journal of Software Engineering and Knowledge Engineering 17(1): 57-78 (2007) |
| 2006 |
|---|
| 2 | EE | Pao-Ann Hsiung,
Shang-Wei Lin,
Yean-Ru Chen,
Chun-Hsian Huang,
Jia-Jen Yeh,
Hong-Yu Sun,
Chao-Sheng Lin,
Hsiao-Win Liao:
Model Checking Timed Systems with Urgencies.
ATVA 2006: 67-81 |
| 2005 |
|---|
| 1 | EE | Shang-Wei Lin,
Pao-Ann Hsiung,
Chun-Hsian Huang,
Yean-Ru Chen:
Model Checking Prioritized Timed Automata.
ATVA 2005: 370-384 |
