| * | 2009 |
|---|
| 8 | EE | Hsiu-Cheng Chang,
Yao-Chang Yang,
Jia-Wei Chen,
Ching-Lung Su,
Cheng-An Chien,
Jiun-In Guo,
Jinn-Shyan Wang:
A dynamic quality-scalable H.264 video encoder chip.
ASP-DAC 2009: 125-126 |
| 2007 |
|---|
| 7 | EE | Chun-Hao Chang,
Jia-Wei Chen,
Hsiu-Cheng Chang,
Yao-Chang Yang,
Jinn-Shyan Wang,
Jiun-In Guo:
A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons.
SiPS 2007: 521-526 |
| 2006 |
|---|
| 6 | EE | Jia-Wei Chen,
Chun-Hao Chang,
Chien-Chang Lin,
Yi-Huan Yang,
Jiun-In Guo,
Jinn-Shyan Wang:
A Condition-based Intra Prediction Algorithm for H.264/AVC.
ICME 2006: 1077-1080 |
| 5 | EE | Jia-Wei Chen,
Kuan-Hung Chen,
Jinn-Shyan Wang,
Jiun-In Guo:
A performance-aware IP core design for multimode transform coding using scalable-DA algorithm.
ISCAS 2006 |
| 2005 |
|---|
| 4 | EE | Kuan-Hung Chen,
Jiun-In Guo,
Jinn-Shyan Wang,
Ching-Wei Yeh,
Jia-Wei Chen:
An Energy-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms.
IEEE Trans. Circuits Syst. Video Techn. 15(5): 704-715 (2005) |
| 2004 |
|---|
| 3 | | Rei-Chin Ju,
Jia-Wei Chen,
Jiun-In Guo,
Tien-Fu Chen:
A parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT.
ISCAS (2) 2004: 769-772 |
| 2 | EE | Jiun-In Guo,
Rei-Chin Ju,
Jia-Wei Chen:
An efficient 2-D DCT/IDCT core design using cyclic convolution and adder-based realization.
IEEE Trans. Circuits Syst. Video Techn. 14(4): 416-428 (2004) |
| 2003 |
|---|
| 1 | EE | Jiun-In Guo,
Jia-Wei Chen,
Han-Chen Chen:
A new 2-D 8/spl times/8 DCT/IDT core design using group distributed arithmetic.
ISCAS (2) 2003: 752-755 |
