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Charlie Chung-Ping Chen Vis

Chung-Ping Chen

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*2008
71EESanghamitra Roy, Yu Hen Hu, Charlie Chung-Ping Chen, Shih-Pin Hung, Tse-Yu Chiang, Jiuan-Guei Tseng: An optimal algorithm for sizing sequential circuits for industrial library based designs. ASP-DAC 2008: 148-151
70EETuck Boon Chan, Hsin-Chia Lu, Jun-Kuei Zeng, Charlie Chung-Ping Chen: LTCC spiral inductor modeling, synthesis, and optimization. ASP-DAC 2008: 768-771
69EEJui-Hsiang Liu, Ming-Feng Tsai, Lumdo Chen, Charlie Chung-Ping Chen: Accurate and analytical statistical spatial correlation modeling for VLSI DFM applications. DAC 2008: 694-697
68EEJun-Kuei Zeng, Chung-Ping Chen: Deep Submicron Interconnect Timing Model with Quadratic Random Variable Analysis. DATE 2008: 1091-1094
67EEJui-Hsiang Liu, Jun-Kuei Zeng, Ai-Syuan Hong, Lumdo Chen, Charlie Chung-Ping Chen: Process-Variation Statistical Modeling for VLSI Timing Analysis. ISQED 2008: 730-733
66EEChung-Ping Chen, Ying-Wen Bai, Yin-Sheng Lee: Performance measurement and queueing analysis of medium-high blocking probability of two and three parallel connection servers. LCN 2008: 568-569
2007
65EESanghamitra Roy, Charlie Chung-Ping Chen: SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design. ASP-DAC 2007: 559-564
64EEDongkeun Oh, Charlie Chung-Ping Chen, Yu Hen Hu: 3DFFT: Thermal Analysis of Non-Homogeneous IC Using 3D FFT Green Function Method. ISQED 2007: 567-572
63EESanghamitra Roy, Weijen Chen, Charlie Chung-Ping Chen, Yu Hen Hu: Numerically Convex Forms and Their Application in Gate Sizing. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1637-1647 (2007)
2006
62EELizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen: Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops. ASP-DAC 2006: 941-946
61EELizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen: Statistical timing analysis with path reconvergence and spatial correlations. DATE 2006: 528-532
60EEPei-Yu Huang, Yu-Min Lee, Jeng-Liang Tsai, Charlie Chung-Ping Chen: Simultaneous area minimization and decaps insertion for power delivery network using adjoint sensitivity analysis with IEKS method. ISCAS 2006
59EELizheng Zhang, Jun Shao, Charlie Chung-Ping Chen: Non-gaussian statistical parameter modeling for SSTA with confidence interval analysis. ISPD 2006: 33-38
58EESanghamitra Roy, Charlie Chung-Ping Chen: ConvexSmooth: A simultaneous convex fitting and smoothing algorithm for convex optimization problems. ISQED 2006: 665-670
57EELizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen: Correlation-Preserved Statistical Timing With a Quadratic Form of Gaussian Variables. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2437-2449 (2006)
56EELizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen: Statistical static timing analysis with conditional linear MAX/MIN approximation and extended canonical timing model. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1183-1191 (2006)
2005
55EEVikas Sharma, Chien-Liang Chen, Chung-Ping Chen: 1-V 7-mW dual-band fast-locked frequency synthesizer. ACM Great Lakes Symposium on VLSI 2005: 431-435
54EERong Jiang, Charlie Chung-Ping Chen: Comprehensive frequency dependent interconnect extraction and evaluation methodology. ASP-DAC 2005: 1070-1073
53EEJeng-Liang Tsai, Charlie Chung-Ping Chen: Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling. ASP-DAC 2005: 1168-1171
52EELizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen: Wave-pipelined on-chip global interconnect. ASP-DAC 2005: 127-132
51EELizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen: Block based statistical timing analysis with extended canonical timing model. ASP-DAC 2005: 250-253
50EEHsinwei Chou, Yu-Hao Wang, Charlie Chung-Ping Chen: Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation. ASP-DAC 2005: 381-386
49EERong Jiang, Yi-Hao Chang, Charlie Chung-Ping Chen: ICCAP: a linear time sparse transformation and reordering algorithm for 3D BEM capacitance extraction. DAC 2005: 163-166
48EELizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen: Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model. DAC 2005: 83-88
47EELizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen: Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model. DATE 2005: 952-957
46 Rong Jiang, Wenyin Fu, Janet Meiling Wang, Vince Lin, Charlie Chung-Ping Chen: Efficient statistical capacitance variability modeling with orthogonal principle factor analysis. ICCAD 2005: 683-690
45 Janet Meiling Wang, Bharat Srinivas, Dongsheng Ma, Charlie Chung-Ping Chen, Jun Li: System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS). ICCAD 2005: 728-735
44EEJeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja: False Path and Clock Scheduling Based Yield-Aware Gate Sizing. VLSI Design 2005: 423-426
43EEJeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja: Yield-Driven, False-Path-Aware Clock Skew Scheduling. IEEE Design & Test of Computers 22(3): 214-222 (2005)
42EERong Jiang, Wenyin Fu, Charlie Chung-Ping Chen: EPEEC: comprehensive SPICE-compatible reluctance extraction for high-speed interconnects above lossy multilayer substrates. IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1562-1571 (2005)
41EEYu-Min Lee, Yahong Cao, Tsung-Hao Chen, Janet Meiling Wang, Charlie Chung-Ping Chen: HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery. IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 797-806 (2005)
2004
40EEClement Luk, Tsung-Hao Chen, Charlie Chung-Ping Chen: Frequency-dependent reluctance extraction. ASP-DAC 2004: 792-797
39EELizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen: Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining. DAC 2004: 904-907
38EERong Jiang, Charlie Chung-Ping Chen: Realizable Reduction for Electromagnetically Coupled RLMC Interconnects. DATE 2004: 1400-1401
37EETing-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen: Thermal and Power Integrity Based Power/Ground Networks Optimization. DATE 2004: 830-835
36EERong Jiang, Charlie Chung-Ping Chen: SCORE: SPICE COmpatible Reluctance Extraction. DATE 2004: 948-953
35EEJeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja: A yield improvement methodology using pre- and post-silicon statistical clock scheduling. ICCAD 2004: 611-618
34EETing-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen: Sensitivity guided net weighting for placement driven synthesis. ISPD 2004: 124-131
33EETing-Yuan Wang, Charlie Chung-Ping Chen: SPICE-Compatible Thermal Simulation with Lumped Circuit Modeling for Thermal Reliability Analysis Based on Modeling Order Reduction. ISQED 2004: 357-362
32EEJeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen: Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 565-572 (2004)
2003
31EEYu-Min Lee, Charlie Chung-Ping Chen: The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method . DATE 2003: 11020-11025
30EETsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen: SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation. ICCAD 2003: 786-792
29EERong Jiang, Tsung-Hao Chen, Charlie Chung-Ping Chen: PODEA: Power delivery efficient analysis with realizable model reduction. ISCAS (4) 2003: 608-611
28EETing-Yuan Wang, Yu-Min Lee, Charlie Chung-Ping Chen: 3D thermal-ADI: an efficient chip-level transient thermal simulator. ISPD 2003: 10-17
27EEJeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen: Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time. ISPD 2003: 166-173
26EETing-Yuan Wang, Charlie Chung-Ping Chen: Thermal-ADI - a linear-time chip-level dynamic thermal-simulation algorithm based on alternating-direction-implicit (ADI) method. IEEE Trans. VLSI Syst. 11(4): 691-700 (2003)
25EEYu-Min Lee, Charlie Chung-Ping Chen: The power grid transient simulation in linear time based on 3-D alternating-direction-implicit method. IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1545-1550 (2003)
24EETsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen: INDUCTWISE: inductance-wise interconnect simulator and extractor. IEEE Trans. on CAD of Integrated Circuits and Systems 22(7): 884-894 (2003)
2002
23EEYahong Cao, Yu-Min Lee, Tsung-Hao Chen, Charlie Chung-Ping Chen: HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery. DAC 2002: 379-384
22EETsung-Hao Chen, Clement Luk, Hyungsuk Kim, Charlie Chung-Ping Chen: INDUCTWISE: inductance-wise interconnect simulator and extractor. ICCAD 2002: 215-220
21EETing-Yuan Wang, Charlie Chung-Ping Chen: Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm. ISQED 2002: 157-162
20EECharlie Chung-Ping Chen, Ed Cheng: Future SoC Design Challenges and Solutions (invited). ISQED 2002: 534-538
19EEYu-Min Lee, Charlie Chung-Ping Chen: Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method. IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1343-1352 (2002)
18EETing-Yuan Wang, Charlie Chung-Ping Chen: 3-D Thermal-ADI: a linear-time chip level transient thermal simulator. IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1434-1445 (2002)
2001
17EEYu-Min Lee, Charlie Chung-Ping Chen: Hierarchical model order reduction for signal-integrity interconnect synthesis. ACM Great Lakes Symposium on VLSI 2001: 109-114
16EEYu-Min Lee, Hing Yin Lai, Charlie Chung-Ping Chen: Optimal spacing and capacitance padding for general clock structures. ASP-DAC 2001: 115-119
15EETsung-Hao Chen, Charlie Chung-Ping Chen: Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods. DAC 2001: 559-562
14EEYu-Min Lee, Charlie Chung-Ping Chen: Power Grid Transient Simulation in Linear Time Based on Transmission-Line-Modeling Alternating-Direction-Implicit Method. ICCAD 2001: 75-
13 Pradeepsunder Ganesh, Charlie Chung-Ping Chen: RC-in RC-out Model Order Reduction Accurate up to Second Order Moments. ICCD 2001: 505-506
12 Saisanthosh Balakrishnan, Jong Hyuk Park, Hyungsuk Kim, Yu-Min Lee, Charlie Chung-Ping Chen: Linear Time Hierarchical Capacitance Extraction without Multipole Expansion. ICCD 2001: 98-103
11EETing-Yuan Wang, Charlie Chung-Ping Chen: Thermal-ADI: a linear-time chip-level dynamic thermal simulation algorithm based on alternating-direction-implicit (ADI) method. ISPD 2001: 238-243
2000
10 Charlie Chung-Ping Chen, Tae-Woo Lee, Narayanan Murugesan, Susan C. Hagness: Generalized FDTD-ADI: An Unconditionally Stable Full-Wave Maxwell's Equations Solver for VLSI Interconnect Modeling. ICCAD 2000: 156-163
1999
9EEChung-Ping Chen, Noel Menezes: Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching. DAC 1999: 502-506
8EEChung-Ping Chen, D. F. Wong: Error Bounded Padé Approximation via Bilinear Conformal Transformation. DAC 1999: 7-12
7EENoel Menezes, Chung-Ping Chen: Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect. VLSI Design 1999: 476-
6EEChung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong: Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. IEEE Trans. on CAD of Integrated Circuits and Systems 18(7): 1014-1025 (1999)
1998
5EEChung-Ping Chen, Chris C. N. Chu, D. F. Wong: Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. ICCAD 1998: 617-624
1997
4EEChung-Ping Chen, D. F. Wong: Optimal Wire-Sizing Function with Fringing Capacitance Consideration. DAC 1997: 604-607
1996
3EEChung-Ping Chen, Yao-Wen Chang, D. F. Wong: Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. DAC 1996: 405-408
2EEChung-Ping Chen, Yao-Ping Chen, D. F. Wong: Optimal Wire-Sizing Formular Under the Elmore Delay Model. DAC 1996: 487-490
1EEChung-Ping Chen, Hai Zhou, D. F. Wong: Optimal non-uniform wire-sizing under the Elmore delay model. ICCAD 1996: 38-43

Coauthor Index

1Ying-Wen Bai [66]
2Dong Hyun Baik [35] [43] [44]
3Saisanthosh Balakrishnan [12]
4Yahong Cao [23] [41]
5Tuck Boon Chan [70]
6Yao-Wen Chang [3]
7Yi-Hao Chang [49]
8Chien-Liang Chen [55]
9Lumdo Chen [67] [69]
10Tsung-Hao Chen [15] [22] [23] [24] [27] [29] [30] [32] [40] [41]
11Weijen Chen [47] [48] [56] [57] [62] [63]
12Yao-Ping Chen [2]
13Ed Cheng [20]
14Tse-Yu Chiang [71]
15Hsinwei Chou [50]
16Chris C. N. Chu (Chris Chu, Chris Chong-Nuen Chu) [5] [6]
17Wenyin Fu [42] [46]
18Pradeepsunder Ganesh [13]
19John A. Gubner [48] [57]
20Susan C. Hagness [10]
21Ai-Syuan Hong [67]
22Yu Hen Hu [63] [64] [71]
23Yuhen Hu [39] [47] [48] [51] [52] [56] [57] [61] [62]
24Pei-Yu Huang [60]
25Shih-Pin Hung [71]
26Rong Jiang [29] [36] [38] [42] [46] [49] [54]
27Hyungsuk Kim [12] [22]
28Hing Yin Lai [16]
29Tae-Woo Lee [10]
30Yin-Sheng Lee [66]
31Yu-Min Lee [12] [14] [16] [17] [19] [23] [25] [28] [31] [41] [60]
32Jun Li [45]
33Vince Lin [46]
34Jui-Hsiang Liu [67] [69]
35Hsin-Chia Lu [70]
36Clement Luk [22] [24] [30] [40]
37Dongsheng Ma [45]
38Noel Menezes [7] [9]
39Narayanan Murugesan [10]
40Dongkeun Oh [64]
41Jong Hyuk Park [12]
42Sanghamitra Roy [58] [63] [65] [71]
43Kewal K. Saluja [35] [43] [44]
44Jun Shao [59]
45Vikas Sharma [55]
46Bharat Srinivas [45]
47Jeng-Liang Tsai [27] [32] [34] [35] [37] [43] [44] [53] [60] [62]
48Ming-Feng Tsai [69]
49Jiuan-Guei Tseng [71]
50Janet Meiling Wang (Janet Meiling Wang Roveda) [41] [45] [46]
51Ting-Yuan Wang [11] [18] [21] [26] [28] [33] [34] [37]
52Yu-Hao Wang [50]
53Martin D. F. Wong (D. F. Wong) [1] [2] [3] [4] [5] [6] [8]
54Jun-Kuei Zeng [67] [68] [70]
55Lizheng Zhang [39] [47] [48] [51] [52] [56] [57] [59] [61] [62]
56Hai Zhou [1]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)