Pramit Chavda
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1998
1
EE
Pramit Chavda,
James Jacob
,
Vishwani D. Agrawal
: Optimizing Logic Design Using Boolean Transforms.
VLSI Design 1998
: 218-221
Coauthor Index
1
Vishwani D. Agrawal
[
1
]
2
James Jacob
[
1
]
Copyright ©
Tue Nov 3 08:52:44 2009 by
Michael Ley
(
ley@uni-trier.de
)
