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Si-En Chang Vis

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*1997
4EEShyh-An Chi, R.-Ming Shiu, Jih-Ching Chiu, Si-En Chang, Chung-Ping Chung: Instruction Cache Prefetching with Extended BTB. ICPADS 1997: 360-
1994
3 Si-En Chang, Chia-Chang Hsu: Efficient Simulation Methods for Multi-Level Cache Memory Hierarchies. HICSS (1) 1994: 221-230
1990
2EESi-En Chang, M. L. Manwaring, Y. Paul Chiang: Extended restricted AND-parallelism execution model. SPDP 1990: 471-474
1989
1 Si-En Chang, Y. Paul Chiang: Restricted AND-Parallelism Execution Model with Side-Effects. NACLP 1989: 350-368

Coauthor Index

1Shyh-An Chi [4]
2Y. Paul Chiang [1] [2]
3Jih-Ching Chiu [4]
4Chung-Ping Chung [4]
5Chia-Chang Hsu [3]
6M. L. Manwaring [2]
7R.-Ming Shiu [4]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)