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Shih-Chieh Chang Vis

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*2009
63EEYu-Min Kuo, Yue-Lung Chang, Shih-Chieh Chang: Efficient Boolean Characteristic Function for Timed Automatic Test Pattern Generation. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 417-425 (2009)
62EEYu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska: Spare Cells With Constant Insertion for Engineering Change. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 456-460 (2009)
2008
61EECheng-Tao Hsieh, Jason Cong, Zhiru Zhang, Shih-Chieh Chang: Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA. ASP-DAC 2008: 10-15
60EEYu-Min Kuo, Shih-Hung Weng, Shih-Chieh Chang: A novel sequential circuit optimization with clock gating logic. ICCAD 2008: 230-233
59EEShih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang, Malgorzata Marek-Sadowska: Timing analysis considering IR drop waveforms in power gating designs. ICCD 2008: 532-537
58EEYu-Shih Su, Po-Hsien Chang, Shih-Chieh Chang, TingTing Hwang: Synthesis of a novel timing-error detection architecture. ACM Trans. Design Autom. Electr. Syst. 13(1): (2008)
2007
57EECheng-Hung Lin, Yu-Tang Tai, Shih-Chieh Chang: Optimization of pattern matching algorithm for memory based architecture. ANCS 2007: 11-16
56EEDe-Shiuan Chiou, Da-Cheng Juan, Yu-Ting Chen, Shih-Chieh Chang: Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization. DAC 2007: 81-86
55EEYu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska: An Efficient Mechanism for Performance Optimization of Variable-Latency Designs. DAC 2007: 976-981
54EEYu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska: Engineering change using spare cells with constant insertion. ICCAD 2007: 544-547
53EEYu-Ting Chen, Da-Cheng Juan, Ming-Chao Lee, Shih-Chieh Chang: An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon. ICCAD 2007: 779-782
52EEAida Todri, Malgorzata Marek-Sadowska, Shih-Chieh Chang: Analysis and optimization of power-gated ICs with multiple power gating configurations. ICCAD 2007: 783-790
51EEAida Todri, Shih-Chieh Chang, Malgorzata Marek-Sadowska: Electromigration and voltage drop aware power grid optimization for power gated ICs. ISLPED 2007: 391-394
50EEYu-Min Kuo, Cheng-Hung Lin, Chun-Yao Wang, Shih-Chieh Chang, Pei-Hsin Ho: Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure. ISQED 2007: 344-349
49EECheng-Tao Hsieh, Jian-Cheng Lin, Shih-Chieh Chang: Efficient Transition-Mode Boolean Characteristic Function with Its Application to Maximum Instantaneous Current Analysis. ISQED 2007: 602-606
48EECheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang: Optimization of Pattern Matching Circuits for Regular Expression on FPGA. IEEE Trans. VLSI Syst. 15(12): 1303-1310 (2007)
2006
47EEKai-Chiang Wu, Cheng-Tao Hsieh, Shih-Chieh Chang: Delay variation tolerance for domino circuits. ASP-DAC 2006: 354-359
46EEDe-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh: Timing driven power gating. DAC 2006: 121-124
45EECheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang: Optimization of regular expression pattern matching circuits on FPGA. DATE Designers' Forum 2006: 12-17
44EEYu-Min Kuo, Yue-Lung Chang, Shih-Chieh Chang: Efficient Boolean characteristic function for fast timed ATPG. ICCAD 2006: 96-99
43EEYi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chieh Chang, Yung-Chih Chen: Language-Based High Level Transaction Extraction on On-chip Buses. ISQED 2006: 231-236
42EEZhong-Zhen Wu, Shih-Chieh Chang: Multiple wire reconnections based on implication flow graph. ACM Trans. Design Autom. Electr. Syst. 11(4): 939-952 (2006)
41EETzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh: Power minimization for dynamic PLAs. IEEE Trans. VLSI Syst. 14(6): 616-624 (2006)
2005
40EECheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang, Wen-Ben Jone: Design and design automation of rectification logic for engineering change. ASP-DAC 2005: 1006-1009
39EETzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh: Power minimization for dynamic PLAs. ASP-DAC 2005: 1010-1013
38EEYen-Fong Lee, Shi-Yu Huang, Sheng-Yu Hsu, I-Ling Chen, Cheng-Tao Shieh, Jian-Cheng Lin, Shih-Chieh Chang: Power estimation starategies for a low-power security processor. ASP-DAC 2005: 367-371
37EEWai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu, Shih-Chieh Chang: FPGA technology mapping optimization by rewiring algorithms. ISCAS (6) 2005: 5653-5656
2004
36EES. Ghosh, K. W. Lai, Wen-Ben Jone, Shih-Chieh Chang: Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits. Asian Test Symposium 2004: 210-215
35EEShih-Chieh Chang, Cheng-Tao Hsieh, Kai-Chiang Wu: Re-synthesis for delay variation tolerance. DAC 2004: 814-819
34EECheng-Tao Hsieh, Jian-Cheng Lin, Shih-Chieh Chang: A vectorless estimation of maximum instantaneous current for sequential circuits. ICCAD 2004: 537-540
2003
33EEJ. H. Jiang, Wen-Ben Jone, Shih-Chieh Chang, S. Ghosh: Embedded core test generation using broadcast test architecture and netlist scrambling. IEEE Transactions on Reliability 52(4): 435-443 (2003)
2002
32EETzyy-Kuen Tien, Tong-Kai Tsai, Shih-Chieh Chang: Crosstalk Alleviation for Dynamic PLAs. DATE 2002: 683-689
31EEJiann-Chyi Rau, Y. M. Chen, Shih-Chieh Chang: A don't-care based image circuit for function verification. ISCAS (5) 2002: 325-328
30EETzyy-Kuen Tien, Shih-Chieh Chang, Tong-Kai Tsai: Crosstalk alleviation for dynamic PLAs. IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1416-1424 (2002)
2001
29EEJ. H. Jiang, Shih-Chieh Chang, Wen-Ben Jone: Embedded Core Testing Using Broadcast Test Architecture. DFT 2001: 95-103
28EEShih-Chieh Chang, Jiann-Chyi Rau: A timing-driven pseudoexhaustive testing for VLSI circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 147-158 (2001)
27EEShih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang: Charge-sharing alleviation and detection for CMOS domino circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 266-280 (2001)
26EEShih-Chieh Chang, Zhong-Zhen Wu: Theorems and extensions of single wire replacement. IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1159-1164 (2001)
2000
25EEYin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang: Novel techniques for improving testability analysis. Asian Test Symposium 2000: 392-397
24EEChing-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang: Charge sharing fault analysis and testing for CMOS domino logic circuits. Asian Test Symposium 2000: 435-440
23EEChing-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone: Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits. DFT 2000: 329-337
22 Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang: Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. ICCAD 2000: 387-390
21 Shih-Chieh Chang, Zhong-Zhen Wu, He-Zhe Yu: Wire Reconnections Based on Implication Flow Graph. ICCAD 2000: 533-536
20EEShih-Chieh Chang, Wen-Ben Jone, Shi-Sen Chang: TAIR: testability analysis by implication reasoning. IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 152-160 (2000)
1999
19EEChing-Wei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone: Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications. DAC 1999: 68-71
18EEChing-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone: Charge Sharing Fault Detection for CMOS Domino Logic Circuits. DFT 1999: 77-85
17EEShih-Chieh Chang, Jung-Cheng Chuang, Zhong-Zhen Wu: Synthesis for multiple input wires replacement of a gate for wiring consideration. ICCAD 1999: 115-119
16EEChingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone: Power reduction through iterative gate sizing and voltage scaling. ISCAS (1) 1999: 246-249
15 Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska: Circuit Optimization by Rewiring. IEEE Trans. Computers 48(9): 962-970 (1999)
14EEShih-Chieh Chang, David Ihsin Cheng: Efficient Boolean division and substitution using redundancy addition and removing. IEEE Trans. on CAD of Integrated Circuits and Systems 18(8): 1096-1106 (1999)
1998
13EEShih-Chieh Chang, David Ihsin Cheng: Efficient Boolean Division and Substitution. DAC 1998: 342-347
12EEWen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu: A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits. ITC 1998: 322-330
11EEShih-Chieh Chang, Shi-Sen Chang, Wen-Ben Jone, Chien-Chung Tsai: A novel combinational testability analysis by considering signal correlation. ITC 1998: 658-667
1997
10EEShih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska: Postlayout logic restructuring using alternative wires. IEEE Trans. on CAD of Integrated Circuits and Systems 16(6): 587-596 (1997)
1996
9EEShih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska: Fast Boolean optimization by rewiring. ICCAD 1996: 262-269
8EEShih-Chieh Chang, Malgorzata Marek-Sadowska, TingTing Hwang: Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams. IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1226-1236 (1996)
7EEShih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng: Perturb and simplify: multilevel Boolean network optimizer. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1494-1504 (1996)
1995
6EEChih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng: Logic Synthesis for Engineering Change. DAC 1995: 647-652
5EEShih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng: An Efficient Algorithm for Local Don't Care Sets Calculation. DAC 1995: 663-667
1994
4EEShih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska: Layout Driven Logic Synthesis for FPGAs. DAC 1994: 308-313
3 Shih-Chieh Chang, David Ihsin Cheng, Malgorzata Marek-Sadowska: Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions. EDAC-ETC-EUROASIC 1994: 620-624
2EEShih-Chieh Chang, Malgorzata Marek-Sadowska: Perturb and simplify: multi-level boolean network optimizer. ICCAD 1994: 2-5
1992
1 Shih-Chieh Chang, Malgorzata Marek-Sadowska: Technology Mapping via Transformations of Function Graphs. ICCD 1992: 159-162

Coauthor Index

1Min-Cheng Chang [16] [19]
2Po-Hsien Chang [58]
3Shi-Sen Chang [11] [20]
4Ya-Ting Chang [54] [62]
5Yue-Lung Chang [44] [63]
6I-Ling Chen [38]
7Kuang-Chien Chen [6]
8Shih-Hsin Chen [46]
9Y. M. Chen [31]
10Yu-Ting Chen [53] [56]
11Yung-Chih Chen [43]
12Ching-Hwa Cheng [18] [22] [23] [24] [25] [27]
13David Ihsin Cheng [3] [13] [14]
14Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng) [4] [5] [6] [7] [10]
15De-Shiuan Chiou [46] [56]
16Jung-Cheng Chuang [17]
17Jason Cong [61]
18S. Ghosh [33] [36]
19Lukas P. P. P. van Ginneken [9] [15]
20Pei-Hsin Ho [50]
21Cheng-Tao Hsieh [34] [35] [47] [49] [61]
22Sheng-Yu Hsu [38]
23Chih-Tsun Huang [45] [48]
24Shi-Yu Huang [38]
25Yi-Le Huang [43]
26Yung-Chang Huang [40]
27TingTing Hwang [8] [58]
28Chang-Ping Jiang [45] [48]
29J. H. Jiang [29] [33]
30Wen-Ben Jone [11] [12] [16] [18] [19] [20] [22] [23] [24] [27] [29] [33] [36] [40]
31Da-Cheng Juan [53] [56]
32Yu-Min Kuo [44] [50] [54] [59] [60] [62] [63]
33K. W. Lai [36]
34Ming-Chao Lee [53]
35Shin-De Lee [27]
36Yen-Fong Lee [38]
37Shin-De Li [22]
38Cheng-Hung Lin [40] [45] [48] [50] [57]
39Chih-Chang Lin [6]
40Jian-Cheng Lin [34] [38] [49]
41Wing-Hang Lo [37]
42Malgorzata Marek-Sadowska [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [15] [51] [52] [54] [55] [59] [62]
43Jiann-Chyi Rau [12] [28] [31]
44Cheng-Tao Shieh [38]
45Yin-He Su [25]
46Yu-Shih Su [55] [58]
47Yu-Tang Tai [57]
48Wai-Chung Tang [37]
49Tzyy-Kuen Tien [30] [32] [39] [41]
50Aida Todri [51] [52]
51Chien-Chung Tsai [11]
52Chih-Shen Tsai [39] [41]
53Tong-Kai Tsai [30] [32]
54Chun-Yao Wang [43] [50]
55Da-Chung Wang [55]
56Jinn-Shyan Wang [18] [22] [23] [24] [27]
57Shih-Hung Weng [59] [60]
58Nam Sung Woo [4] [10]
59Kai-Chiang Wu [35] [47]
60Yu-Liang Wu (David Yu-Liang Wu) [12] [37]
61Zhong-Zhen Wu [17] [21] [26] [42]
62Chingwei Yeh (Ching-Wei Yeh) [16] [19] [39] [41] [46]
63Richard Yeh [43]
64He-Zhe Yu [21]
65Zhiru Zhang [61]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)