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Sreejit Chakravarty Vis

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*2009
75EEFan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz: Detectability of internal bridging faults in scan chains. ASP-DAC 2009: 678-683
74EENicholas Callegari, Pouria Bastani, Li-C. Wang, Sreejit Chakravarty, Alexander Tetelbaum: Path selection for monitoring unexpected systematic timing effects. ASP-DAC 2009: 781-786
2008
73EEFan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz: Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. DFT 2008: 394-402
72EEI-De Huang, Yi-Shing Chang, Sandeep K. Gupta, Sreejit Chakravarty: An Industrial Case Study of Sticky Path-Delay Faults. VTS 2008: 395-402
71EEFan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz: On the Detectability of Scan Chain Internal Faults — An Industrial Case Study. VTS 2008: 79-84
70EEAbhijit Jas, Yi-Shing Chang, Sreejit Chakravarty: A Methodology for Handling Complex Functional Constraints for Large Industrial Designs. J. Electronic Testing 24(1-3): 259-269 (2008)
2006
69EEAbhijit Jas, Yi-Shing Chang, Sreejit Chakravarty: An Approach to Minimizing Functional Constraints. DFT 2006: 215-226
68EESuriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty: Path Delay Fault Simulation on Large Industrial Designs. VTS 2006: 16-23
67EEEric N. Tran, Vishwashanth Kasulasrinivas, Sreejit Chakravarty: Silicon Evaluation of Logic Proximity Bridge Patterns. VTS 2006: 78-85
66EEMahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi: Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2954-2964 (2006)
2005
65EESreejit Chakravarty: Improving Logic Test Quality of Microprocessors. Asian Test Symposium 2005
64EEManan Syal, Michael S. Hsiao, Suriyaprakash Natarajan, Sreejit Chakravarty: Untestable Multi-Cycle Path Delay Faults in Industrial Designs. Asian Test Symposium 2005: 194-201
63EEMahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi: Implicit and Exact Path Delay Fault Grading in Sequential Circuits. DATE 2005: 990-995
62EEYi-Shing Chang, Sreejit Chakravarty, Hiep Hoang, Nick Thorpe, Khen Wee: Transition Tests for High Performance Microprocessors. VTS 2005: 29-34
61EESreejit Chakravarty, Yi-Shing Chang, Hiep Hoang, Sridhar Jayaraman, Silvio Picano, Cheryl Prunty, Eric W. Savage, Rehan Sheikh, Eric N. Tran, Khen Wee: Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor. VTS 2005: 337-342
60EEXiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran: Efficient techniques for transition testing. ACM Trans. Design Autom. Electr. Syst. 10(2): 258-278 (2005)
2004
59EEManan Syal, Michael S. Hsiao, Sreejit Chakravarty: Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks. ITC 2004: 1034-1043
58EESreejit Chakravarty, Eric W. Savage, Eric N. Tran: Defect Coverage Analysis of Partitioned Testing. ITC 2004: 907-915
57EESujit T. Zachariah, Sreejit Chakravarty: Extraction of two-node bridges from large industrial circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 433-439 (2004)
2003
56EEManan Syal, Michael S. Hsiao, Kiran B. Doreswamy, Sreejit Chakravarty: Efficient Implication - Based Untestable Bridge Fault Identifier. VTS 2003: 393-402
55EESujit T. Zachariah, Sreejit Chakravarty: Algorithm to extract two-node bridges. IEEE Trans. VLSI Syst. 11(4): 741-744 (2003)
54EEXiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran: Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors. J. Electronic Testing 19(4): 437-445 (2003)
2002
53EESreejit Chakravarty: Supplemental Test Methods (Tutorial Abstract). ISQED 2002: 7
52EESreejit Chakravarty, Ankur Jain, Nandakumar Radhakrishnan, Eric W. Savage, Sujit T. Zachariah: Experimental Evaluation of Scan Tests for Bridges. ITC 2002: 509-518
51EEXiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran: Techniques to Reduce Data Volume and Application Time for Transition Test. ITC 2002: 983-992
50EESreejit Chakravarty, Kambiz Komeyli, Eric W. Savage, Michael J. Carruthers, Bret T. Stastny, Sujit T. Zachariah: Layout Analysis to Extract Open Nets Caused by Systematic Failure Mechanisms. VTS 2002: 367-372
49EESreejit Chakravarty, Ankur Jain: Fault Models for Speed Failures Caused by Bridges and Opens. VTS 2002: 373-378
2001
48EESujit T. Zachariah, Sreejit Chakravarty: A Novel Algorithm for Multi-Node Bridge Analysis of Large VLSI Circuits. VLSI Design 2001: 333-338
47EEIsmed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Janak H. Patel, Sreejit Chakravarty: Diagnostic simulation of stuck-at faults in sequential circuits using compact lists. ACM Trans. Design Autom. Electr. Syst. 6(4): 471-489 (2001)
46EEKamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty: Automatic generation and compaction of March tests for memory arrays. IEEE Trans. VLSI Syst. 9(6): 845-857 (2001)
2000
45EESujit T. Zachariah, Sreejit Chakravarty, Carl D. Roth: A novel algorithm to extract two-node bridges. DAC 2000: 790-793
44 Seonki Kim, Sreejit Chakravarty, Bapiraju Vinnakota: An analysis of the delay defect detection capability of the ECR test method. ITC 2000: 1060-1069
43 Sujit T. Zachariah, Sreejit Chakravarty: A scalable and efficient methodology to extract two node bridges from large industrial circuits. ITC 2000: 750-759
42EESreejit Chakravarty, Sujit T. Zachariah: STBM: a fast algorithm to simulate IDDQ tests forleakage faults. IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 568-576 (2000)
1999
41EESreenivas Mandava, Sreejit Chakravarty, Sandip Kundu: On Detecting Bridges Causing Timing Failures. ICCD 1999: 400-406
40 Sujit T. Zachariah, Sreejit Chakravarty: A Comparative Study of Pseudo Stuck-At and Leakage Fault Model. VLSI Design 1999: 91-94
39EESreejit Chakravarty, Vinodh Gopal: Techniques to Encode and Compress Fault Dictionaries. VTS 1999: 195-200
1998
38EEKamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty: A new framework for generating optimal March tests for memory arrays. ITC 1998: 73-
37EEVinay Dabholkar, Sreejit Chakravarty: Computing Stress Tests for Gate Oxide Shorts. VLSI Design 1998: 378-391
36EEVinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, Sudhakar M. Reddy: Techniques for minimizing power dissipation in scan and combinational circuits during test application. IEEE Trans. on CAD of Integrated Circuits and Systems 17(12): 1325-1333 (1998)
35EEYiming Gong, Sreejit Chakravarty: Locating bridging faults using dynamically computed stuck-at fault dictionaries. IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 876-887 (1998)
1997
34EEVinay Dabholkar, Sreejit Chakravarty: Computing stress tests for interconnect defects. Asian Test Symposium 1997: 143-148
33EESreejit Chakravarty: On the capability of delay tests to detect bridges and opens. Asian Test Symposium 1997: 314-319
32EEYiming Gong, Sreejit Chakravarty: Using fault sampling to compute I/sub DDQ/ diagnostic test set. VTS 1997: 74-79
31EEPaul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel: Algorithms to compute bridging fault coverage of IDDQ test sets. ACM Trans. Design Autom. Electr. Syst. 2(3): 281-305 (1997)
1996
30EEPaul J. Thadikaran, Sreejit Chakravarty: Fast Algorithms for Computer IDDQ Tests for Combination Circuits. VLSI Design 1996: 103-106
29EESreejit Chakravarty: A sampling technique for diagnostic fault simulation. VTS 1996: 192-197
28 Sreejit Chakravarty, Paul J. Thadikaran: Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits. IEEE Trans. Computers 45(10): 1131-1140 (1996)
27 Sreejit Chakravarty: A Study of Theoretical Issues in the Synthesis of Delay Fault Testability Circuits. IEEE Trans. Computers 45(8): 985-991 (1996)
26EESreejit Chakravarty, Yiming Gong, Srikanth Venkataraman: Diagnostic simulation of stuck-at faults in combinational circuits. J. Electronic Testing 8(1): 87-97 (1996)
25EESreejit Chakravarty, Paul J. Thadikaran: Algorithms to select IDDQ measurement points to detect bridging faults. J. Electronic Testing 8(3): 275-285 (1996)
1995
24EESrikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs, Elizabeth M. Rudnick, Sreejit Chakravarty, Janak H. Patel: Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists. DAC 1995: 133-138
23 Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel: Fault Simulation ofIDDQ Tests for Bridging Faults in Sequential Circuits. FTCS 1995: 340-349
22EEYiming Gong, Sreejit Chakravarty: On adaptive diagnostic test generation. ICCAD 1995: 181-184
21EESreejit Chakravarty, Yiming Gong: Voting model based diagnosis of bridging faults in combinational circuits. VLSI Design 1995: 338-342
20EEVinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel: Cyclic stress tests for full scan circuits. VTS 1995: 89-94
19 Sreejit Chakravarty, Ramalingam Sridhar, Shambhu J. Upadhyaya, Yervant Zorian, Gil Philips, Bozena Kaminska, Bernard Courtois: Conference Reports. IEEE Design & Test of Computers 12(4): 95-97 (1995)
1994
18 Sreejit Chakravarty, Paul J. Thadikaran: A Study of IDDQ Subset Selection Algorithms for Bridging Faults. ITC 1994: 403-412
17 Sreejit Chakravarty, Sivaprakasam Suresh: IDDQ Measurement Based Diagnosis of Bridging Faults in Full Scan Circuits. VLSI Design 1994: 179-182
1993
16EESreejit Chakravarty, Yiming Gong: An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational Circuits. DAC 1993: 520-524
15 Sreejit Chakravarty: A Characterization of Binary Decision Diagrams. IEEE Trans. Computers 42(2): 129-137 (1993)
1992
14EESreejit Chakravarty, Minsheng Liu: Algorithms for Current Monitor Based Diagnosis of Bridging and Leakage Faults. DAC 1992: 353-356
13EESreejit Chakravarty, Minsheng Liu: Algorithms for IDDQ measurement based diagnosis of bridging faults. J. Electronic Testing 3(4): 377-385 (1992)
1991
12EESreejit Chakravarty, Xin He, S. S. Ravi: Minimum area layout of series-parallel transistor networks is NP-hard. IEEE Trans. on CAD of Integrated Circuits and Systems 10(7): 943-949 (1991)
11EESreejit Chakravarty: A characterization of robust test-pairs for stuck-open faults. J. Electronic Testing 1(4): 275-286 (1991)
1990
10EESreejit Chakravarty: On Synthesizing and Identifying Stuck-Open Testable CMOS Combinational Circuits (extended abstract). DAC 1990: 736-739
9 Ajay Shekhawat, Sreejit Chakravarty: Heuristics for the MSC Problem for Serial and Shared-Memory Computers. ICPP (3) 1990: 64-67
8 Sreejit Chakravarty, Harry B. Hunt III: On Computing Signal Probability and Detection Probability of Stuck-at Faults. IEEE Trans. Computers 39(11): 1369-1377 (1990)
7EESreejit Chakravarty, S. S. Ravi: Computing optimal test sequences from complete test sets for stuck-open faults in CMOS circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 9(3): 329-331 (1990)
1989
6 Sreejit Chakravarty: A Testable Realization of CMOS Combinational Circuits. ITC 1989: 509-518
5 Sreejit Chakravarty, Harry B. Hunt III: A Note on Detecting Sneak Paths in Transistor Networks. IEEE Trans. Computers 38(6): 861-864 (1989)
4 Sreejit Chakravarty, Harry B. Hunt III, S. S. Ravi, Daniel J. Rosenkrantz: The Complexity of Generating Minimum Test Sets for PLA's and Monotone Combinational Circuits. IEEE Trans. Computers 38(6): 865-869 (1989)
3EESreejit Chakravarty: On the complexity of computing tests for CMOS gates. IEEE Trans. on CAD of Integrated Circuits and Systems 8(9): 973-980 (1989)
1988
2 Sreejit Chakravarty, Shambhu J. Upadhyaya: A Unified Approach to Designing Fault-Tolerant Processor Ensembles. ICPP (1) 1988: 339-342
1986
1 Sreejit Chakravarty, Harry B. Hunt III: On the Computation of Detection Probability for Multiple Faults. ITC 1986: 252-262

Coauthor Index

1Pouria Bastani [74]
2Nicholas Callegari [74]
3Michael J. Carruthers [50]
4Yi-Shing Chang [61] [62] [69] [70] [72]
5Bernard Courtois [19]
6Vinay Dabholkar [20] [34] [36] [37]
7Narendra Devta-Prasanna [71] [73] [75]
8Kiran B. Doreswamy [56]
9W. Kent Fuchs [24] [47]
10Yiming Gong [16] [21] [22] [26] [32] [35]
11Vinodh Gopal [39]
12Sandeep K. Gupta [72]
13Ismed Hartanto [24] [47]
14Xin He [12]
15Hiep Hoang [61] [62]
16Michael S. Hsiao [51] [54] [56] [59] [60] [64]
17I-De Huang [72]
18Harry B. Hunt III [1] [4] [5] [8]
19Ankur Jain [49] [52]
20Abhijit Jas [69] [70]
21Rathish Jayabharathi [63] [66]
22Sridhar Jayaraman [61]
23Bozena Kaminska [19]
24Vishwashanth Kasulasrinivas [67]
25Seonki Kim [44]
26Kambiz Komeyli [50]
27Mahilchi Milir Vaseekar Kumar [63] [66]
28Sandip Kundu [41]
29Minsheng Liu [13] [14]
30Xiao Liu [51] [54] [60]
31Sreenivas Mandava [41]
32J. Najm [20]
33Suriyaprakash Natarajan [64] [68]
34Janak H. Patel [20] [23] [24] [31] [47]
35Srinivas Patil [68]
36Gil Philips [19]
37Silvio Picano [61]
38Irith Pomeranz [36] [71] [73] [75]
39Cheryl Prunty [61]
40Nandakumar Radhakrishnan [52]
41S. S. Ravi [4] [7] [12]
42Sudhakar M. Reddy [36] [71] [73] [75]
43Daniel J. Rosenkrantz [4]
44Carl D. Roth [45]
45Elizabeth M. Rudnick [24] [47]
46Eric W. Savage [50] [52] [58] [61]
47Rehan Sheikh [61]
48Ajay Shekhawat [9]
49Ramalingam Sridhar [19]
50Bret T. Stastny [50]
51Sivaprakasam Suresh [17]
52Manan Syal [56] [59] [64]
53Alexander Tetelbaum [74]
54Paul J. Thadikaran [18] [23] [25] [28] [30] [31] [51] [54] [60]
55Nick Thorpe [62]
56Spyros Tragoudas [63] [66]
57Eric N. Tran [58] [61] [67]
58Shambhu J. Upadhyaya [2] [19] [38] [46]
59Srikanth Venkataraman [24] [26] [47]
60Bapiraju Vinnakota [44]
61Li-C. Wang [74]
62Khen Wee [61] [62]
63Fan Yang [71] [73] [75]
64Sujit T. Zachariah [40] [42] [43] [45] [48] [50] [52] [55] [57]
65Kamran Zarrineh [38] [46]
66Yervant Zorian [19]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)