dblp.uni-trier.dewww.uni-trier.de

Srimat T. Chakradhar Vis

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeerX - CSB - MetaPress - Google - Bing - Yahoo

*2009
100EEMurugan Sankaradass, Venkata Jakkula, Srihari Cadambi, Srimat T. Chakradhar, Igor Durdanovic, Eric Cosatto, Hans Peter Graf: A Massively Parallel Coprocessor for Convolutional Neural Networks. ASAP 2009: 53-60
99EENarayanan Sundaram, Anand Raghunathan, Srimat T. Chakradhar: A framework for efficient and scalable execution of domain-specific templates on GPUs. IPDPS 2009: 1-12
98EEJiayuan Meng, Srimat T. Chakradhar, Anand Raghunathan: Best-effort parallel execution framework for Recognition and mining applications. IPDPS 2009: 1-12
2008
97EEJanar Thoguluva, Anand Raghunathan, Srimat T. Chakradhar: Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor. DATE 2008: 1148-1153
96EENupur Kothari, Kiran Nagaraja, Vijay Raghunathan, Florin Sultan, Srimat T. Chakradhar: HERMES: A Software Architecture for Visibility and Control in Wireless Sensor Network Deployments. IPSN 2008: 395-406
95EEHans Peter Graf, Srihari Cadambi, Igor Durdanovic, Venkata Jakkula, Murugan Sankaradass, Eric Cosatto, Srimat T. Chakradhar: A Massively Parallel Digital Learning Processor. NIPS 2008: 529-536
2007
94EESeongmoon Wang, Wenlong Wei, Srimat T. Chakradhar: Unknown blocking scheme for low control data volume and high observability. DATE 2007: 33-38
93EEMango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei: A hybrid scheme for compacting test responses with unknown values. ICCAD 2007: 513-519
92EERajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell: Zero Cost Test Point Insertion Technique for Structured ASICs. VLSI Design 2007: 357-363
91EEDivya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar: Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. IEEE Trans. VLSI Syst. 15(6): 699-710 (2007)
2006
90EEMango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei: Unknown-tolerance analysis and test-quality control for test response compaction using space compactors. DAC 2006: 1083-1088
89EEDivya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar: Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. DAC 2006: 496-501
88EESeongmoon Wang, Kedarnath J. Balakrishnan, Srimat T. Chakradhar: Efficient unknown blocking using LFSR reseeding. DATE 2006: 1051-1052
87EEMango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei, Kwang-Ting Cheng: Coverage loss by using space compactors in presence of unknown values. DATE 2006: 1053-1054
86EEJahangir Hasan, Srihari Cadambi, Venkata Jakkula, Srimat T. Chakradhar: Chisel: A Storage-efficient, Collision-free Hash-based Network Processing Architecture. ISCA 2006: 203-215
85EEHaris Lekatsas, Jörg Henkel, Venkata Jakkula, Srimat T. Chakradhar: Using Shiftable Content Addressable Memories to Double Memory Capacity on Embedded Systems. VLSI Design 2006: 639-644
84EEKedarnath J. Balakrishnan, Seongmoon Wang, Srimat T. Chakradhar: PIDISC: Pattern Independent Design Independent Seed Compression Technique. VLSI Design 2006: 811-817
83EEJiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar: A design methodology for application-specific networks-on-chip. ACM Trans. Embedded Comput. Syst. 5(2): 263-280 (2006)
82EELoganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar: Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2193-2206 (2006)
81EESeongmoon Wang, Srimat T. Chakradhar: A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1555-1564 (2006)
2005
80EEJoel Coburn, Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar: SECA: security-enhanced communication architecture. CASES 2005: 78-89
79EELei Yang, Robert P. Dick, Haris Lekatsas, Srimat T. Chakradhar: CRAMES: compressed RAM for embedded systems. CODES+ISSS 2005: 93-98
78 Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng: Response shaper: a novel technique to enhance unknown tolerance for output response compaction. ICCAD 2005: 80-87
77EEMango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng: ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values. ICCD 2005: 147-152
76EEJiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar: H.264 HDTV Decoder Using Application-Specific Networks-On-Chip. ICME 2005: 1508-1511
75EEJiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar: A methodology for design, modeling, and analysis of networks-on-chip. ISCAS (2) 2005: 1778-1781
74EEHaris Lekatsas, Jörg Henkel, Venkata Jakkula, Srimat T. Chakradhar: A Unified Architecture for Adaptive Compression of Data and Code on Embedded Systems. VLSI Design 2005: 117-123
73EEWei Li, Seongmoon Wang, Srimat T. Chakradhar, Sudhakar M. Reddy: Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage. VLSI Design 2005: 471-478
72EENikhil Bansal, Kanishka Lahiri, Anand Raghunathan, Srimat T. Chakradhar: Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models. VLSI Design 2005: 579-585
71EELoganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar: Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. VLSI Design 2005: 65-70
70EETiehan Lv, Jiang Xu, Wayne Wolf, Burak Ozer, Jörg Henkel, Srimat T. Chakradhar: A Methodology for Architectural Design of Multimedia Multiprocessor SoCs. IEEE Design & Test of Computers 22(1): 18-26 (2005)
2004
69EESeongmoon Wang, Srimat T. Chakradhar, Kedarnath J. Balakrishnan: Re-configurable embedded core test protocol. ASP-DAC 2004: 234-237
68EESrimat T. Chakradhar: Open architecture test system: not why but when! ASP-DAC 2004: 337-340
67EESeongmoon Wang, Xiao Liu, Srimat T. Chakradhar: Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets. DATE 2004: 1296-1301
66EEJiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar, Tiehan Lv: A Case Study in Networks-on-Chip Design for Embedded Video. DATE 2004: 770-777
65EESrivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar: Tamper Resistance Mechanisms for Secure, Embedded Systems. VLSI Design 2004: 605-
64EEJörg Henkel, Wayne Wolf, Srimat T. Chakradhar: On-chip networks: A scalable, communication-centric embedded system design paradigm. VLSI Design 2004: 845-
63EEHaris Lekatsas, Jörg Henkel, Srimat T. Chakradhar, Venkata Jakkula: Cypress: Compression and Encryption of Data and Code for Embedded Multimedia Systems. IEEE Design & Test of Computers 21(5): 406-415 (2004)
2003
62EEHaris Lekatsas, Jörg Henkel, Srimat T. Chakradhar, Venkata Jakkula, Murugan Sankaradass: CoCo: a hardware/software platform for rapid prototyping of code compression technologies. DAC 2003: 306-311
61EESeongmoon Wang, Srimat T. Chakradhar: A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs. ITC 2003: 574-583
60EESrivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar: Embedding Security in Wireless Embedded Systems. VLSI Design 2003: 269-270
59EESrivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar: Efficient RTL Power Estimation for Large Designs. VLSI Design 2003: 431-439
2001
58EENachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar: Accurate Power Macro-modeling Techniques for Complex RTL Circuits. VLSI Design 2001: 235-241
2000
57EESurendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy: Resource-Constrained Compaction of Sequential Circuit Test Sets. VLSI Design 2000: 398-405
56EEMichael S. Hsiao, Srimat T. Chakradhar: Test Set Compaction Using Relaxed Subsequence Removal. J. Electronic Testing 16(4): 319-327 (2000)
55EEMichael S. Hsiao, Srimat T. Chakradhar: Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits. J. Electronic Testing 16(4): 329-338 (2000)
54EESurendra Bommu, Kiran B. Doreswamy, Srimat T. Chakradhar: A Practical Vector Restoration Technique for Large Sequential Circuits. J. Electronic Testing 16(5): 521-539 (2000)
53EEAngela Krstic, Srimat T. Chakradhar, Kwang-Ting Cheng: Testable Path Delay Fault Cover for Sequential Circuits. J. Inf. Sci. Eng. 16(5): 673-686 (2000)
1999
52EEAngela Krstic, Kwang-Ting (Tim) Cheng, Srimat T. Chakradhar: Testing High Speed VLSI Devices Using Slower Testers. VTS 1999: 16-21
51EESrimat T. Chakradhar, Sujit Dey: Resynthesis and retiming for optimum partial scan. IEEE Trans. on CAD of Integrated Circuits and Systems 18(5): 621-630 (1999)
50EEAngela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar: Primitive delay faults: identification, testing, and design for testability. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 669-684 (1999)
1998
49EEMichael S. Hsiao, Srimat T. Chakradhar: Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits. Asian Test Symposium 1998: 452-457
48EESurendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy: Vector Restoration Using Accelerated Validation and Refinement. Asian Test Symposium 1998: 458-466
47EEMichael S. Hsiao, Srimat T. Chakradhar: State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits. DATE 1998: 577-582
46EESurendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy: Static compaction using overlapped restoration and segment pruning. ICCAD 1998: 140-146
45EESurendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy: Static test sequence compaction based on segment reordering and accelerated vector restoration. ITC 1998: 954-
44EEArun Balakrishnan, Srimat T. Chakradhar: Peripheral Partitioning and Tree Decomposition for Partial Scan. VLSI Design 1998: 181-186
1997
43 Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar: Design for Primitive Delay Fault Testability. ITC 1997: 436-445
42EESrimat T. Chakradhar, Vijay Gangaram, Steven G. Rothweiler: Deriving Signal Constraints to Accelerate Sequential Test Generation. VLSI Design 1997: 488-494
41EESrimat T. Chakradhar, Anand Raghunathan: Bottleneck removal algorithm for dynamic compaction in sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1157-1172 (1997)
40EESrimat T. Chakradhar, Steven G. Rothweiler, Vishwani D. Agrawal: Redundancy removal and test generation for circuits with non-Boolean primitives. IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1370-1377 (1997)
1996
39 Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar: Identification and Test Generation for Primitive Faults. ITC 1996: 423-432
38EEArun Balakrishnan, Srimat T. Chakradhar: Sequential Circuits with combinational Test Generation Complexity. VLSI Design 1996: 111-117
37EEAnand Raghunathan, Srimat T. Chakradhar: Dynamic test Sequence compaction for Sequential Circuits. VLSI Design 1996: 170-173
36EESavita Banerjee, Srimat T. Chakradhar, Rabindra K. Roy: Synchronous Test Generation Model for Asynchronous Circuits. VLSI Design 1996: 178-185
35EEArun Balakrishnan, Srimat T. Chakradhar: Retiming with logic duplication transformation: theory and an application to partial scan. VLSI Design 1996: 296-302
34EESrimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan: Synthesis of initializable asynchronous circuits. IEEE Trans. VLSI Syst. 4(2): 254-263 (1996)
33EESavita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar: Initialization issues in asynchronous circuit synthesis. J. Electronic Testing 9(3): 237-250 (1996)
1995
32EEArun Balakrishnan, Srimat T. Chakradhar: Software transformations for sequential test generation. Asian Test Symposium 1995: 266-
31EESrimat T. Chakradhar, Anand Raghunathan: Bottleneck removal algorithm for dynamic compaction and test cycles reduction. EURO-DAC 1995: 98-104
30EEAnand Raghunathan, Srimat T. Chakradhar: Acceleration techniques for dynamic vector compaction. ICCAD 1995: 310-317
29EESrimat T. Chakradhar: Optimum retiming of large sequential circuits. VLSI Design 1995: 135-140
28EEArun Balakrishnan, Srimat T. Chakradhar: Partial scan design for technology mapped circuits. VLSI Design 1995: 283-287
27EESrimat T. Chakradhar, Steven G. Rothweiler: Redundancy Removal and Test Generation for Circuits with Non-Boolean Primitives. VTS 1995: 12-19
26EESuman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal: A partition and resynthesis approach to testable design of large circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(10): 1268-1276 (1995)
25EESrimat T. Chakradhar, Mahesh A. Iyer, Vishwani D. Agrawal: Energy models for delay testing. IEEE Trans. on CAD of Integrated Circuits and Systems 14(6): 728-739 (1995)
24EESuman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal: Test function embedding algorithms with application to interconnected finite state machines. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1115-1127 (1995)
23EEVishwani D. Agrawal, Srimat T. Chakradhar: Combinational ATPG theorems for identifying untestable faults in sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1155-1160 (1995)
22EESujit Dey, Srimat T. Chakradhar: Design of testable sequential circuits by repositioning flip-flops. J. Electronic Testing 7(1-2): 105-114 (1995)
21EESrimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal: An exact algorithm for selecting partial scan flip-flops. J. Electronic Testing 7(1-2): 83-93 (1995)
1994
20EESrimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal: An Exact Algorithm for Selecting Partial Scan Flip-Flops. DAC 1994: 81-86
19EESrimat T. Chakradhar, Sujit Dey: Resynthesis and Retiming for Optimum Partial Scan. DAC 1994: 87-93
18 Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan: Signal Transition Graph Transformations for Initializability. EDAC-ETC-EUROASIC 1994: 670
17 Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan: Initialization Isuues in the Synthesis of Asynchronous Circuits. ICCD 1994: 447-452
16 Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal: A Test Function Architecture for Interconnected Finite State Machines. VLSI Design 1994: 113-116
15 Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan: Synthesis of Initializable Asynchronous Circuits. VLSI Design 1994: 383-388
14EESrimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell: Energy minimization and design for testability. J. Electronic Testing 5(1): 57-66 (1994)
1993
13EESrimat T. Chakradhar, Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler: Sequential Circuit Delay optimization Using Global Path Delays. DAC 1993: 483-489
12 Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal: A Synthesis Approach to Design for Testability. ITC 1993: 754-763
11EESrimat T. Chakradhar, Vishwani D. Agrawal, Steven G. Rothweiler: A transitive closure algorithm for test generation. IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 1015-1028 (1993)
10EESrimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal: Finite state machine synthesis with fault tolerant test function. J. Electronic Testing 4(1): 57-69 (1993)
1992
9EESrimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal: Finite State Machine Synthesis with Fault Tolerant Test Function. DAC 1992: 562-567
8EESrimat T. Chakradhar, Michael L. Bushnell: A solvable class of quadratic 0-1 programming. Discrete Applied Mathematics 36(3): 233-251 (1992)
7EEVishwani D. Agrawal, Srimat T. Chakradhar: Performance Analysis of Synchronized Iterative Algorithms on Multiprocessor Systems. IEEE Trans. Parallel Distrib. Syst. 3(6): 739-746 (1992)
1991
6EESrimat T. Chakradhar, Vishwani D. Agrawal: A Transitive Closure Based Algorithm for Test Generation. DAC 1991: 353-358
1990
5EESrimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell: Automatic Test Generation Using Quadratic 0-1 Programming. DAC 1990: 654-659
4 Vishwani D. Agrawal, Srimat T. Chakradhar: Logic Simulation and Parallel Processing. ICCAD 1990: 496-499
3EEVishwani D. Agrawal, Srimat T. Chakradhar: Performance estimation in a massively parallel system. SC 1990: 306-313
2EESrimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell, Thomas K. Truong: Neural Net and Boolean Satisfiability Models of Logic Circuits. IEEE Design & Test of Computers 7(5): 54-57 (1990)
1EESrimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal: Toward massively parallel automatic test generation. IEEE Trans. on CAD of Integrated Circuits and Systems 9(9): 981-994 (1990)

Coauthor Index

1Vishwani D. Agrawal [1] [2] [3] [4] [5] [6] [7] [9] [10] [11] [12] [14] [16] [20] [21] [23] [24] [25] [26] [40]
2Divya Arora [89] [91]
3Arun Balakrishnan [20] [21] [28] [32] [35] [38] [44]
4Kedarnath J. Balakrishnan [69] [84] [88]
5Savita Banerjee [15] [17] [18] [33] [34] [36]
6Nikhil Bansal [72]
7Surendra Bommu [45] [46] [48] [54] [57]
8Michael L. Bushnell [1] [2] [5] [8] [14] [92]
9Srihari Cadambi [86] [95] [100]
10Mango Chia-Tso Chao [77] [78] [87] [90] [93]
11Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng) [39] [43] [50] [52] [53] [77] [78] [87] [90] [93]
12Joel Coburn [80]
13Eric Cosatto [95] [100]
14Sujit Dey [13] [19] [22] [51]
15Robert P. Dick [79]
16Kiran B. Doreswamy [45] [46] [48] [54] [57]
17Igor Durdanovic [95] [100]
18Vijay Gangaram [42]
19Hans Peter Graf [95] [100]
20Jahangir Hasan [86]
21Jörg Henkel [62] [63] [64] [66] [70] [74] [75] [76] [83] [85]
22Michael S. Hsiao [47] [49] [55] [56] [58]
23Mahesh A. Iyer [25]
24Venkata Jakkula [62] [63] [74] [85] [86] [95] [100]
25Niraj K. Jha [71] [82] [89] [91]
26Suman Kanjilal [9] [10] [12] [16] [24] [26]
27Nupur Kothari [96]
28Angela Krstic [39] [43] [50] [52] [53]
29Kanishka Lahiri [72]
30Ganesh Lakshminarayana [58]
31Haris Lekatsas [62] [63] [74] [79] [85]
32Wei Li [73]
33Loganathan Lingappan [71] [82]
34Xiao Liu [67]
35Tiehan Lv [66] [70]
36Jiayuan Meng [98]
37Kiran Nagaraja [96]
38Burak Ozer [70]
39Miodrag Potkonjak [13]
40Nachiketh R. Potlapally [58]
41Dhiraj K. Pradhan [15] [17] [18] [34]
42Anand Raghunathan [30] [31] [37] [41] [58] [59] [60] [65] [71] [72] [80] [82] [89] [91] [97] [98] [99]
43Vijay Raghunathan [96]
44Srivaths Ravi [59] [60] [65] [71] [80] [82] [89] [91]
45Sudhakar M. Reddy [73]
46Steven G. Rothweiler [11] [13] [27] [40] [42]
47Rabindra K. Roy [15] [17] [18] [33] [34] [36]
48Murugan Sankaradass [62] [89] [91] [95] [100]
49Rajamani Sethuram [92]
50Florin Sultan [96]
51Narayanan Sundaram [99]
52Janar Thoguluva [97]
53Thomas K. Truong [2]
54Seongmoon Wang [61] [67] [69] [73] [77] [78] [81] [84] [87] [88] [90] [92] [93] [94]
55Wenlong Wei [87] [90] [93] [94]
56Wayne Wolf [64] [66] [70] [75] [76] [83]
57Jiang Xu [66] [70] [75] [76] [83]
58Lei Yang [79]

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)