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Stephen Dean Brown Vis

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*2009
50EEAndrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour: Towards automated ECOs in FPGAs. FPGA 2009: 3-12
2008
49EEAndrew C. Ling, Jianwen Zhu, Stephen Dean Brown: Delay driven AIG restructuring using slack budget management. ACM Great Lakes Symposium on VLSI 2008: 163-166
48EETomasz S. Czajkowski, Stephen Dean Brown: Functionally linear decomposition and synthesis of logic circuits for FPGAs. DAC 2008: 18-23
47EEFranjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown: Towards Compilation of Streaming Programs into FPGA Hardware. FDL 2008: 67-72
46EETomasz S. Czajkowski, Stephen Dean Brown: Fast toggle rate computation for FPGA circuits. FPL 2008: 65-70
45EETomasz S. Czajkowski, Stephen Dean Brown: Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2236-2249 (2008)
44EEAndrew C. Ling, Jianwen Zhu, Stephen Dean Brown: Scalable Synthesis and Clustering Techniques Using Decision Diagrams. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 423-435 (2008)
2007
43EEAndrew C. Ling, Jianwen Zhu, Stephen Dean Brown: BddCut: Towards Scalable Symbolic Cut Enumeration. ASP-DAC 2007: 408-413
42EETomasz S. Czajkowski, Stephen Dean Brown: Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits. DAC 2007: 324-329
41 Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown: On Digital Search Trees - A Simple Method for Constructing Balanced Binary Trees. ICSOFT (PL/DPS/KE/MUSE) 2007: 61-68
40EEAndrew C. Ling, Deshanand P. Singh, Stephen Dean Brown: Incremental placement for structured ASICs using the transportation problem. VLSI-SoC 2007: 172-177
39EEValavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown: Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. IEEE Trans. VLSI Syst. 15(8): 895-903 (2007)
38EEAndrew C. Ling, Deshanand P. Singh, Stephen Dean Brown: FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1196-1210 (2007)
37EEDeshanand P. Singh, Stephen Dean Brown: An area-efficient timing closure technique for FPGAs using Shannon's expansion. Integration 40(2): 167-173 (2007)
2006
36EEBlair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown: A Multithreaded Soft Processor for SoPC Area Reduction. FCCM 2006: 131-142
35EEMehrdad Eslami Dehkordi, Stephen Dean Brown, Terry Borer: Modular Partitioning for Incremental Compilation. FPL 2006: 1-6
34EEValavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic: Adaptive FPGAs: High-Level Architecture and a Synthesis Method. FPL 2006: 1-8
33EEGordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown: Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. ICCAD 2006: 135-142
32EEValavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown: Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. SLIP 2006: 3-8
31EEValavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic: Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2331-2340 (2006)
2005
30EEAndrew C. Ling, Deshanand P. Singh, Stephen Dean Brown: FPGA technology mapping: a study of optimality. DAC 2005: 427-432
29EEDeshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown: Incremental retiming for FPGA physical synthesis. DAC 2005: 433-438
28 Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown: FPGA PLB Evaluation using Quantified Boolean Satisfiability. FPL 2005: 19-24
27 Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown: Post-Placement BDD-Based Decomposition for FPGAs. FPL 2005: 31-38
26EEFranjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen Dean Brown: Experiences with Soft-Core Processor Design. IPDPS 2005
25EEAndrew C. Ling, Deshanand P. Singh, Stephen Dean Brown: FPGA Logic Synthesis Using Quantified Boolean Satisfiability. SAT 2005: 444-450
2003
24EEMehrdad Eslami Dehkordi, Stephen Dean Brown: Recursive circuit clustering for minimum delay and area. FPGA 2003: 242
23 Deshanand P. Singh, Terry P. Borer, Stephen Dean Brown: Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices. VLSI 2003: 28-33
22 Deshanand P. Singh, Stephen Dean Brown: An Area-Efficient Timing Closure Technique for FPGAs Using Shannon's Expansion. VLSI 2003: 41-50
2002
21EEDeshanand P. Singh, Stephen Dean Brown: Constrained clock shifting for field programmable gate arrays. FPGA 2002: 121-126
20EEDeshanand P. Singh, Stephen Dean Brown: Integrated retiming and placement for field programmable gate arrays. FPGA 2002: 67-76
19EEValavan Manohararajah, Terry Borer, Stephen Dean Brown, Zvonko G. Vranesic: Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. FPL 2002: 232-241
18EEDeshanand P. Singh, Stephen Dean Brown: Incremental placement for layout driven optimizations on FPGAs. ICCAD 2002: 752-759
2001
17EEDeshanand P. Singh, Stephen Dean Brown: The case for registered routing switches in field programmable gate arrays. FPGA 2001: 161-169
2000
16EEAlireza Kaviani, Stephen Dean Brown: Technology mapping issues for an FPGA with lookup tables and PLA-like blocks. FPGA 2000: 60-66
15EER. Grindley, Tarek S. Abdelrahman, Stephen Dean Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic: The NUMAchine Multiprocessor. ICPP 2000: 487-496
1999
14EEAlireza Kaviani, Stephen Dean Brown: The Hybrid Field-Programmable Architecture. IEEE Design & Test of Computers 16(2): 74-83 (1999)
1998
13EEA. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic: Design and Implementation of the NUMAchine Multiprocessor. DAC 1998: 66-69
12EEJason Helge Anderson, Stephen Dean Brown: Technology Mapping for Large Complex PLDs. DAC 1998: 698-703
11EEJason Helge Anderson, Stephen Dean Brown: An LPGA with Foldable PLA-style Logic Blocks. FPGA 1998: 244-252
1997
10EEGuy G. Lemieux, Stephen Dean Brown, Daniel Vranesic: On two-step routing for FPGAS. ISPD 1997: 60-66
1996
9EEStephen Dean Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic: Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools. DAC 1996: 427-432
8EEAlireza Kaviani, Stephen Dean Brown: Hybrid FPGA Architecture. FPGA 1996: 3-9
7EEStephen Dean Brown, Jonathan Rose: FPGA and CPLD Architectures: A Tutorial. IEEE Design & Test of Computers 13(2): 42-57 (1996)
6EEStephen Dean Brown, Muhammad M. Khellah, Zvonko G. Vranesic: Minimizing FPGA Interconnect Delays. IEEE Design & Test of Computers 13(4): 16-23 (1996)
5EEStephen Dean Brown: FPGA Architectural Research: A Survey. IEEE Design & Test of Computers 13(4): 9-15 (1996)
1993
4EEStephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic: A stochastic model to predict the routability of field-programmable gate arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1827-1838 (1993)
1992
3 Benjamin Tseng, Jonathan Rose, Stephen Dean Brown: Improving FPGA Routing Architectures Using Architecture and CAD Interactions. ICCD 1992: 99-104
2EEStephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic: A detailed router for field-programmable gate arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 11(5): 620-628 (1992)
1990
1 Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic: A Detailed Router for Field-Programmable Gate Arrays. ICCAD 1990: 382-385

Coauthor Index

1Tarek S. Abdelrahman [15]
2Jason Helge Anderson [11] [12]
3Terry Borer [19] [35]
4Terry P. Borer [23]
5Davor Capalija [36]
6S. Caranci [9] [13] [15]
7Gordon R. Chiu [32] [33] [39]
8Tomasz S. Czajkowski [42] [45] [46] [48]
9D. DeVries [15]
10Mehrdad Eslami Dehkordi [24] [35]
11Blair Fort [26] [36]
12Benjamin Gamsa [15]
13A. Grbic [9] [13] [15]
14R. Grindley [9] [13] [15]
15M. Gusat [9] [13] [15]
16R. Ho [15]
17Alireza Kaviani [8] [14] [16]
18Muhammad M. Khellah [6]
19Orran Krieger [15]
20Guy G. Lemieux [10] [13] [15]
21Andrew C. Ling [25] [28] [30] [38] [40] [43] [44] [49] [50]
22K. Loveless [9] [13] [15]
23Naraig Manjikian [9] [13] [15]
24Valavan Manohararajah [19] [27] [29] [31] [32] [33] [34] [39]
25P. McHardy [15]
26Franjo Plavec [26] [41] [47]
27Jonathan Rose [1] [2] [3] [4] [7]
28Sean Safarpour [50]
29Deshanand P. Singh [17] [18] [20] [21] [22] [23] [25] [27] [28] [29] [30] [32] [33] [37] [38] [39] [40]
30Sinisa Srbljic [9] [13] [15]
31Michael Stumm [13] [15]
32Benjamin Tseng [3]
33Daniel Vranesic [10]
34Zvonko G. Vranesic [1] [2] [4] [6] [9] [13] [15] [19] [26] [31] [34] [36] [41] [47]
35Jianwen Zhu [43] [44] [49] [50]
36Zeljko Zilic [9] [13] [15]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)